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https://github.com/Noratrieb/rustv32i.git
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improve error messages
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parent
78aa1e8d75
commit
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2 changed files with 28 additions and 26 deletions
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@ -1,8 +1,10 @@
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## 2.0.0
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## 0.2.0
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- BREAKING CHANGE: Make `Inst` `#[non_exhaustive]`
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- BREAKING CHANGE: Make `Inst` `#[non_exhaustive]`
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- BREAKING CHANGE: Change immediate fields in `Inst` to `Imm`
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- BREAKING CHANGE: Change immediate fields in `Inst` to `Imm`
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- Improve error messages
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## 0.1.1
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## 0.1.1
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- Add `Fence::is_tso`
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- Add `Fence::is_tso`
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@ -900,7 +900,7 @@ impl Inst {
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src: code.rs2_short(),
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src: code.rs2_short(),
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base: code.rs1_short(),
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base: code.rs1_short(),
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},
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},
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_ => return Err(decode_error(code, "funct3")),
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_ => return Err(decode_error(code, "C0 funct3")),
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},
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},
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// C1
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// C1
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0b01 => match code.funct3() {
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0b01 => match code.funct3() {
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@ -937,7 +937,7 @@ impl Inst {
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// C.SRLI -> srli \rd', \rd', \imm
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// C.SRLI -> srli \rd', \rd', \imm
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0b00 => {
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0b00 => {
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if bit12 != 0 {
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if bit12 != 0 {
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return Err(decode_error(code, "imm"));
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return Err(decode_error(code, "C.SRLI imm"));
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}
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}
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Inst::Srli {
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Inst::Srli {
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@ -949,7 +949,7 @@ impl Inst {
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// C.SRAI -> srai \rd', \rd', \imm
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// C.SRAI -> srai \rd', \rd', \imm
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0b01 => {
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0b01 => {
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if bit12 != 0 {
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if bit12 != 0 {
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return Err(decode_error(code, "imm"));
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return Err(decode_error(code, "C.SRLI imm"));
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}
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}
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Inst::Srai {
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Inst::Srai {
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@ -966,7 +966,7 @@ impl Inst {
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},
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},
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0b11 => {
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0b11 => {
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if bit12 != 0 {
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if bit12 != 0 {
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return Err(decode_error(code, "bit 12"));
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return Err(decode_error(code, "C1 Arith bit 12"));
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}
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}
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let funct2 = code.extract(5..=6);
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let funct2 = code.extract(5..=6);
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match funct2 {
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match funct2 {
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@ -1032,7 +1032,7 @@ impl Inst {
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_ => {
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_ => {
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let uimm = code.immediate_s(&[(2..=6, 12), (12..=12, 17)]);
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let uimm = code.immediate_s(&[(2..=6, 12), (12..=12, 17)]);
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if uimm.as_u32() == 0 {
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if uimm.as_u32() == 0 {
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return Err(decode_error(code, "imm"));
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return Err(decode_error(code, "C.LUI imm"));
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}
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}
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Inst::Lui {
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Inst::Lui {
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uimm,
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uimm,
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@ -1065,7 +1065,7 @@ impl Inst {
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src1: code.rs1_short(),
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src1: code.rs1_short(),
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src2: Reg::ZERO,
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src2: Reg::ZERO,
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},
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},
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_ => return Err(decode_error(code, "funct3")),
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_ => return Err(decode_error(code, "C1 funct3")),
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},
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},
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// C2
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// C2
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0b10 => match code.funct3() {
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0b10 => match code.funct3() {
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@ -1084,7 +1084,7 @@ impl Inst {
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0b010 => {
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0b010 => {
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let dest = code.rd();
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let dest = code.rd();
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if dest.0 == 0 {
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if dest.0 == 0 {
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return Err(decode_error(code, "rd"));
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return Err(decode_error(code, "C.LWSP rd"));
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}
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}
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Inst::Lw {
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Inst::Lw {
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@ -1101,7 +1101,7 @@ impl Inst {
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// C.JR -> jalr zero, 0(\rs1)
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// C.JR -> jalr zero, 0(\rs1)
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(0, _, 0) => {
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(0, _, 0) => {
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if rd_rs1.0 == 0 {
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if rd_rs1.0 == 0 {
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return Err(decode_error(code, "rs1"));
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return Err(decode_error(code, "C.JR rs1"));
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}
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}
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Inst::Jalr {
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Inst::Jalr {
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offset: Imm::ZERO,
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offset: Imm::ZERO,
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@ -1129,7 +1129,7 @@ impl Inst {
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src1: rd_rs1,
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src1: rd_rs1,
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src2: rs2,
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src2: rs2,
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},
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},
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_ => return Err(decode_error(code, "inst")),
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_ => return Err(decode_error(code, "C2 funct=100 inst")),
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}
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}
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}
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}
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// C.SWSP -> sw \reg \offset(sp)
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// C.SWSP -> sw \reg \offset(sp)
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@ -1138,7 +1138,7 @@ impl Inst {
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src: code.rs2(),
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src: code.rs2(),
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base: Reg::SP,
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base: Reg::SP,
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},
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},
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_ => return Err(decode_error(code, "funct3")),
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_ => return Err(decode_error(code, "C2 funct3")),
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},
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},
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_ => return Err(decode_error(code, "instruction is not compressed")),
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_ => return Err(decode_error(code, "instruction is not compressed")),
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};
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};
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@ -1171,7 +1171,7 @@ impl Inst {
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base: code.rs1(),
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base: code.rs1(),
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dest: code.rd(),
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dest: code.rd(),
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},
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},
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_ => return Err(decode_error(code, "funct3")),
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_ => return Err(decode_error(code, "JALR funct3")),
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},
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},
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// BRANCH
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// BRANCH
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0b1100011 => match code.funct3() {
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0b1100011 => match code.funct3() {
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@ -1205,7 +1205,7 @@ impl Inst {
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src1: code.rs1(),
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src1: code.rs1(),
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src2: code.rs2(),
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src2: code.rs2(),
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},
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},
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_ => return Err(decode_error(code, "funct3")),
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_ => return Err(decode_error(code, "BRANCH funct3")),
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},
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},
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// LOAD
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// LOAD
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0b0000011 => match code.funct3() {
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0b0000011 => match code.funct3() {
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@ -1234,7 +1234,7 @@ impl Inst {
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dest: code.rd(),
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dest: code.rd(),
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base: code.rs1(),
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base: code.rs1(),
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},
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},
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_ => return Err(decode_error(code, "funct3")),
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_ => return Err(decode_error(code, "LOAD funct3")),
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},
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},
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// STORE
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// STORE
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0b0100011 => match code.funct3() {
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0b0100011 => match code.funct3() {
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@ -1253,7 +1253,7 @@ impl Inst {
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src: code.rs2(),
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src: code.rs2(),
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base: code.rs1(),
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base: code.rs1(),
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},
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},
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_ => return Err(decode_error(code, "funct3")),
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_ => return Err(decode_error(code, "STORE funct3")),
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},
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},
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// OP-IMM
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// OP-IMM
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0b0010011 => match code.funct3() {
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0b0010011 => match code.funct3() {
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@ -1308,9 +1308,9 @@ impl Inst {
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dest: code.rd(),
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dest: code.rd(),
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src1: code.rs1(),
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src1: code.rs1(),
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},
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},
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_ => return Err(decode_error(code, "funct7")),
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_ => return Err(decode_error(code, "OP-IMM funct7")),
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},
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},
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_ => return Err(decode_error(code, "funct3")),
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_ => return Err(decode_error(code, "OP-IMM funct3")),
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},
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},
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// OP
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// OP
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0b0110011 => {
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0b0110011 => {
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@ -1335,7 +1335,7 @@ impl Inst {
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(0b101, 0b0000001) => Inst::Divu { dest, src1, src2 },
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(0b101, 0b0000001) => Inst::Divu { dest, src1, src2 },
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(0b110, 0b0000001) => Inst::Rem { dest, src1, src2 },
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(0b110, 0b0000001) => Inst::Rem { dest, src1, src2 },
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(0b111, 0b0000001) => Inst::Remu { dest, src1, src2 },
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(0b111, 0b0000001) => Inst::Remu { dest, src1, src2 },
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_ => return Err(decode_error(code, "funct3/funct7")),
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_ => return Err(decode_error(code, "OP funct3/funct7")),
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}
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}
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}
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}
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// MISC-MEM
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// MISC-MEM
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@ -1364,7 +1364,7 @@ impl Inst {
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src: code.rs1(),
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src: code.rs1(),
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},
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},
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},
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},
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_ => return Err(decode_error(code, "funct3")),
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_ => return Err(decode_error(code, "MISC-MEM funct3")),
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}
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}
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}
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}
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// SYSTEM
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// SYSTEM
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@ -1373,25 +1373,25 @@ impl Inst {
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return Err(decode_error(code, "unimp instruction"));
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return Err(decode_error(code, "unimp instruction"));
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}
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}
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if code.rd().0 != 0 {
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if code.rd().0 != 0 {
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return Err(decode_error(code, "rd"));
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return Err(decode_error(code, "SYSTEM rd"));
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}
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}
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if code.funct3() != 0 {
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if code.funct3() != 0 {
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return Err(decode_error(code, "funct3"));
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return Err(decode_error(code, "SYSTEM funct3"));
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}
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}
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if code.rs1().0 != 0 {
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if code.rs1().0 != 0 {
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return Err(decode_error(code, "rs1"));
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return Err(decode_error(code, "SYSTEM rs1"));
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}
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}
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match code.imm_i().as_u32() {
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match code.imm_i().as_u32() {
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0b000000000000 => Inst::Ecall,
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0b000000000000 => Inst::Ecall,
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0b000000000001 => Inst::Ebreak,
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0b000000000001 => Inst::Ebreak,
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_ => return Err(decode_error(code, "imm")),
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_ => return Err(decode_error(code, "SYSTEM imm")),
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}
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}
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}
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}
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// AMO
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// AMO
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0b00101111 => {
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0b00101111 => {
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// width must be W
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// width must be W
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if code.funct3() != 0b010 {
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if code.funct3() != 0b010 {
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return Err(decode_error(code, "funct3"));
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return Err(decode_error(code, "AMO width funct3"));
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}
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}
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let kind = code.extract(27..=31);
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let kind = code.extract(27..=31);
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@ -1404,7 +1404,7 @@ impl Inst {
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// LR
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// LR
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0b00010 => {
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0b00010 => {
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if code.rs2().0 != 0 {
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if code.rs2().0 != 0 {
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return Err(decode_error(code, "rs2"));
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return Err(decode_error(code, "AMO.LR rs2"));
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}
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}
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Inst::LrW {
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Inst::LrW {
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@ -1431,7 +1431,7 @@ impl Inst {
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0b10100 => AmoOp::Max,
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0b10100 => AmoOp::Max,
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0b11000 => AmoOp::Minu,
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0b11000 => AmoOp::Minu,
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0b11100 => AmoOp::Maxu,
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0b11100 => AmoOp::Maxu,
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_ => return Err(decode_error(code, "funct7")),
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_ => return Err(decode_error(code, "AMO op funct7")),
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};
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};
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Inst::AmoW {
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Inst::AmoW {
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order,
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order,
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