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test and fix M

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nora 2025-03-09 20:18:47 +01:00
parent 1d20052465
commit 023d1645cd
2 changed files with 67 additions and 17 deletions
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16
src/emu.rs
View file

@ -107,7 +107,7 @@ impl IndexMut<Reg> for Emulator {
} }
} }
#[derive(Clone, Copy, PartialEq, Eq)] #[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct Reg(pub u32); pub struct Reg(pub u32);
impl Reg { impl Reg {
@ -318,7 +318,8 @@ impl Emulator {
self[dest] = ((self[src1] as i32).wrapping_mul(self[src2] as i32)) as u32; self[dest] = ((self[src1] as i32).wrapping_mul(self[src2] as i32)) as u32;
} }
Inst::Mulh { dest, src1, src2 } => { Inst::Mulh { dest, src1, src2 } => {
let shifted = ((self[src1] as i64).wrapping_mul(self[src2] as i64) as i64) >> 32; let mul_result = (self[src1] as i32 as i64).wrapping_mul(self[src2] as i32 as i64);
let shifted = (mul_result as u64) >> 32;
self[dest] = shifted as u32; self[dest] = shifted as u32;
} }
Inst::Mulhsu { .. } => todo!("mulhsu"), Inst::Mulhsu { .. } => todo!("mulhsu"),
@ -329,7 +330,7 @@ impl Emulator {
Inst::Div { dest, src1, src2 } => { Inst::Div { dest, src1, src2 } => {
if self[src2] == 0 { if self[src2] == 0 {
self[dest] = u32::MAX; self[dest] = u32::MAX;
} else if self[src2] == u32::MAX { } else if self[src1] == i32::MIN as u32 && self[src2] == u32::MAX {
self[dest] = u32::MAX; self[dest] = u32::MAX;
} else { } else {
self[dest] = ((self[src1] as i32) / (self[src2] as i32)) as u32; self[dest] = ((self[src1] as i32) / (self[src2] as i32)) as u32;
@ -337,7 +338,7 @@ impl Emulator {
} }
Inst::Divu { dest, src1, src2 } => { Inst::Divu { dest, src1, src2 } => {
if self[src2] == 0 { if self[src2] == 0 {
self[dest] = 2_u32.pow(32) - 1; self[dest] = u32::MAX;
} else { } else {
self[dest] = self[src1] / self[src2]; self[dest] = self[src1] / self[src2];
} }
@ -345,7 +346,7 @@ impl Emulator {
Inst::Rem { dest, src1, src2 } => { Inst::Rem { dest, src1, src2 } => {
if self[src2] == 0 { if self[src2] == 0 {
self[dest] = self[src1]; self[dest] = self[src1];
} else if self[src2] == u32::MAX { } else if self[src1] == i32::MIN as u32 && self[src2] == u32::MAX {
self[dest] = 0; self[dest] = 0;
} else { } else {
self[dest] = ((self[src1] as i32) % (self[src2] as i32)) as u32; self[dest] = ((self[src1] as i32) % (self[src2] as i32)) as u32;
@ -353,9 +354,10 @@ impl Emulator {
} }
Inst::Remu { dest, src1, src2 } => { Inst::Remu { dest, src1, src2 } => {
if self[src2] == 0 { if self[src2] == 0 {
self[dest] = 2_u32.pow(32) - 1; self[dest] = self[src1];
} else { } else {
self[dest] = self[src1] % self[src2]; dbg!(self[src1], self[src2]);
self[dest] = dbg!(self[src1] % self[src2]);
} }
} }
Inst::AmoW { Inst::AmoW {

68
tests/check/int_comp.S
View file

@ -2,7 +2,7 @@
#include "../helper.S" #include "../helper.S"
.macro CASE_REG inst a b expected .macro CASER inst a b expected
li t0, \a li t0, \a
li t1, \b li t1, \b
\inst t2, t0, t1 \inst t2, t0, t1
@ -16,7 +16,7 @@
.endm .endm
.macro CASE_BOTH inst insti a b expected .macro CASE_BOTH inst insti a b expected
CASE_REG \inst, \a, \b, \expected CASER \inst, \a, \b, \expected
CASE_IMM \insti, \a, \b, \expected CASE_IMM \insti, \a, \b, \expected
.endm .endm
@ -27,6 +27,8 @@
.endm .endm
START_TEST START_TEST
# Base instructions
CASE add 10, 20, 30 CASE add 10, 20, 30
CASE add 10, -2, 8 CASE add 10, -2, 8
CASE add 10, 0, 10 CASE add 10, 0, 10
@ -64,20 +66,20 @@ START_TEST
CASE sll, 0, 10, 0 CASE sll, 0, 10, 0
CASE sll, 10, 0, 10 CASE sll, 10, 0, 10
CASE sll, -1, 31, -2147483648 CASE sll, -1, 31, -2147483648
CASE_REG sll, -1, 32, -1 # error for immediate CASER sll, -1, 32, -1 # error for immediate
CASE srl, 4, 1, 2 CASE srl, 4, 1, 2
CASE srl, 0, 10, 0 CASE srl, 0, 10, 0
CASE srl, 10, 0, 10 CASE srl, 10, 0, 10
CASE srl, -1, 1, 2147483647 CASE srl, -1, 1, 2147483647
CASE srl, 0b111, 2, 0b001 CASE srl, 0b111, 2, 0b001
CASE_REG srl, -1, 32, -1 # error for immediate CASER srl, -1, 32, -1 # error for immediate
CASE_REG sub, 10, 5, 5 CASER sub, 10, 5, 5
CASE_REG sub, -1, 1, -2 CASER sub, -1, 1, -2
CASE_REG sub, 1, 2, -1 CASER sub, 1, 2, -1
CASE_REG sub, -1, -2, 1 CASER sub, -1, -2, 1
CASE_REG sub, 0, 4294967295, 1 CASER sub, 0, 4294967295, 1
CASE sra, 4, 1, 2 CASE sra, 4, 1, 2
CASE sra, 0, 10, 0 CASE sra, 0, 10, 0
@ -85,6 +87,52 @@ START_TEST
CASE sra, -1, 1, -1 CASE sra, -1, 1, -1
CASE sra, -1, 31, -1 CASE sra, -1, 31, -1
CASE sra, 0b111, 2, 0b001 CASE sra, 0b111, 2, 0b001
CASE_REG sra, 10, 32, 10 # error for immediate CASER sra, 10, 32, 10 # error for immediate
# M extension
CASER mul, 4, 4, 16
CASER mul, 10, 0, 0
CASER mul, 10, 1, 10
CASER mul, -1, -1, 1
CASER mul, 25252566, 5225225, 353909638
CASER mulh 4, 4, 0
CASER mulh, -1, -1, 0
CASER mulh, 25252566, 5225225, 30722
CASER mulhu 4, 4, 0
CASER mulhu, -1, -1, 4294967294
CASER mulhu, 25252566, 5225225, 30722
# mulhsu hasn't been implemented yet.
CASER div, 4, 2, 2
CASER div, -1, 1, -1
CASER div, 1, 1, 1
CASER div, 1, 0, -1
CASER div, -10, 2, -5
CASER div, 5, 2, 2
CASER div, 5, -1, -5
CASER div, -2147483648, -1, -1
CASER divu, 4, 2, 2
CASER divu, -1, 1, -1
CASER divu, 1, 1, 1
CASER divu, 1, 0, -1
CASER divu, -10, 2, 2147483643
CASER divu, 5, 2, 2
CASER rem, 4, 2, 0
CASER rem, 5, 2, 1
CASER rem, 5, 0, 5
CASER rem, -10, 3, -1
CASER rem, 5, -1, 0
CASER rem, -2147483648, -1, 0
CASER remu, 4, 2, 0
CASER remu, 5, 2, 1
CASER remu, 5, 0, 5
CASER remu, -10, 3, 0
PASS PASS