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Zihintpause

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nora 2025-03-09 14:55:31 +01:00
parent b8d9f28059
commit 105706e862
3 changed files with 29 additions and 17 deletions
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4
README.md
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@ -7,6 +7,10 @@ A small RISC-V emulator written in Rust.
- [x] Base RV32I instruction set
- [x] M standard extension
- [ ] A standard extension
- [ ] Zalrsc standard extension
- [ ] Zaamo standard extension
- [ ] F standard extension
- [ ] D standard extension
- [ ] C standard extension
- [x] Zihintpause standard extension

4
src/emu.rs
View file

@ -105,10 +105,12 @@ impl IndexMut<Reg> for Emulator {
}
}
#[derive(Clone, Copy)]
#[derive(Clone, Copy, PartialEq, Eq)]
pub struct Reg(pub u32);
impl Reg {
pub const ZERO: Reg = Reg(0);
pub const RA: Reg = Reg(1);
pub const SP: Reg = Reg(2);
// arguments, return values:

38
src/inst.rs
View file

@ -81,6 +81,27 @@ pub struct FenceSet {
pub memory_write: bool,
}
impl Fence {
pub fn is_pause(&self) -> bool {
self.pred
== FenceSet {
device_input: false,
device_output: false,
memory_read: false,
memory_write: true,
}
&& self.succ
== FenceSet {
device_input: false,
device_output: false,
memory_read: false,
memory_write: false,
}
&& self.dest == Reg::ZERO
&& self.src == Reg::ZERO
}
}
impl Debug for Inst {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
Display::fmt(&self, f)
@ -184,22 +205,7 @@ impl Display for Inst {
Inst::And { dest, src1, src2 } => write!(f, "and {dest}, {src1}, {src2}"),
Inst::Fence { fence } => match fence.fm {
0b1000 => write!(f, "fence.TSO"),
0b0000
if fence.pred
== FenceSet {
device_input: false,
device_output: false,
memory_read: false,
memory_write: true,
}
&& fence.succ
== FenceSet {
device_input: false,
device_output: false,
memory_read: false,
memory_write: false,
} =>
{
0b0000 if fence.is_pause() => {
write!(f, "pause")
}
_ => write!(f, "fence {},{}", fence.pred, fence.succ),