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https://github.com/Noratrieb/rustv32i.git
synced 2026-01-14 13:25:01 +01:00
slightly clean up the code
This commit is contained in:
parent
ae29dd0505
commit
13aec667db
4 changed files with 29 additions and 29 deletions
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@ -16,3 +16,7 @@ tempfile = "3.18.0"
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[lints.rust]
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[lints.rust]
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unexpected_cfgs = { level = "warn", check-cfg = ['cfg(slow_tests)'] }
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unexpected_cfgs = { level = "warn", check-cfg = ['cfg(slow_tests)'] }
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[lints.clippy]
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type_complexity = "allow"
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if_same_then_else = "allow"
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@ -30,7 +30,7 @@ pub struct Phdr {
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pub p_align: u32,
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pub p_align: u32,
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}
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}
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impl<'a> Elf<'a> {
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impl Elf<'_> {
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pub fn header(&self) -> Result<Header> {
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pub fn header(&self) -> Result<Header> {
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let (ident, rest) = self.content.split_bytes(16)?;
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let (ident, rest) = self.content.split_bytes(16)?;
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if ident[..4] != *b"\x7fELF" {
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if ident[..4] != *b"\x7fELF" {
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37
src/emu.rs
37
src/emu.rs
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@ -3,7 +3,6 @@ use std::{
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fmt::{Debug, Display},
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fmt::{Debug, Display},
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io::Write,
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io::Write,
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ops::{Index, IndexMut},
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ops::{Index, IndexMut},
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u32,
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};
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};
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pub struct Memory {
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pub struct Memory {
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@ -22,20 +21,18 @@ impl Memory {
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}
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}
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}
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}
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pub fn slice(&self, addr: u32, len: u32) -> Result<&[u8], Status> {
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pub fn slice(&self, addr: u32, len: u32) -> Result<&[u8], Status> {
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Ok(self
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self.mem
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.mem
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.get((addr as usize)..)
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.get((addr as usize)..)
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.ok_or(Status::InvalidMemoryAccess(addr))?
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.ok_or(Status::InvalidMemoryAccess(addr))?
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.get(..(len as usize))
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.get(..(len as usize))
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.ok_or(Status::InvalidMemoryAccess(addr))?)
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.ok_or(Status::InvalidMemoryAccess(addr))
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}
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}
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pub fn slice_mut(&mut self, addr: u32, len: u32) -> Result<&mut [u8], Status> {
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pub fn slice_mut(&mut self, addr: u32, len: u32) -> Result<&mut [u8], Status> {
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Ok(self
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self.mem
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.mem
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.get_mut((addr as usize)..)
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.get_mut((addr as usize)..)
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.ok_or(Status::InvalidMemoryAccess(addr))?
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.ok_or(Status::InvalidMemoryAccess(addr))?
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.get_mut(..(len as usize))
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.get_mut(..(len as usize))
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.ok_or(Status::InvalidMemoryAccess(addr))?)
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.ok_or(Status::InvalidMemoryAccess(addr))
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}
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}
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pub fn load_u8(&self, addr: u32) -> Result<u8, Status> {
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pub fn load_u8(&self, addr: u32) -> Result<u8, Status> {
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@ -48,21 +45,21 @@ impl Memory {
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Ok(u32::from_le_bytes(self.slice(addr, 4)?.try_into().unwrap()))
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Ok(u32::from_le_bytes(self.slice(addr, 4)?.try_into().unwrap()))
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}
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}
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pub fn store_u8(&mut self, addr: u32, value: u8) -> Result<(), Status> {
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pub fn store_u8(&mut self, addr: u32, value: u8) -> Result<(), Status> {
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Ok(self
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self.slice_mut(addr, 1)?
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.slice_mut(addr, 1)?
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.copy_from_slice(&value.to_le_bytes());
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.copy_from_slice(&value.to_le_bytes()))
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Ok(())
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}
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}
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pub fn store_u16(&mut self, addr: u32, value: u16) -> Result<(), Status> {
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pub fn store_u16(&mut self, addr: u32, value: u16) -> Result<(), Status> {
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self.check_align(addr, 2)?;
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self.check_align(addr, 2)?;
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Ok(self
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self.slice_mut(addr, 2)?
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.slice_mut(addr, 2)?
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.copy_from_slice(&value.to_le_bytes());
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.copy_from_slice(&value.to_le_bytes()))
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Ok(())
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}
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}
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pub fn store_u32(&mut self, addr: u32, value: u32) -> Result<(), Status> {
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pub fn store_u32(&mut self, addr: u32, value: u32) -> Result<(), Status> {
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self.check_align(addr, 4)?;
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self.check_align(addr, 4)?;
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Ok(self
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self.slice_mut(addr, 4)?
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.slice_mut(addr, 4)?
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.copy_from_slice(&value.to_le_bytes());
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.copy_from_slice(&value.to_le_bytes()))
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Ok(())
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}
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}
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}
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}
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@ -313,17 +310,17 @@ impl Emulator {
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}
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}
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Inst::Sw { offset, src, base } => {
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Inst::Sw { offset, src, base } => {
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let addr = self[base].wrapping_add(offset);
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let addr = self[base].wrapping_add(offset);
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self.mem.store_u32(addr, self[src] as u32)?;
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self.mem.store_u32(addr, self[src])?;
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}
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}
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Inst::Addi { imm, dest, src1 } => {
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Inst::Addi { imm, dest, src1 } => {
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self[dest] = self[src1].wrapping_add(imm as u32);
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self[dest] = self[src1].wrapping_add(imm);
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}
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}
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Inst::Slti { imm, dest, src1 } => {
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Inst::Slti { imm, dest, src1 } => {
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let result = (self[src1] as i32) < (imm as i32);
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let result = (self[src1] as i32) < (imm as i32);
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self[dest] = result as u32;
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self[dest] = result as u32;
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}
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}
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Inst::Sltiu { imm, dest, src1 } => {
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Inst::Sltiu { imm, dest, src1 } => {
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let result = (self[src1] as u32) < imm as u32;
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let result = self[src1] < imm;
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self[dest] = result as u32;
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self[dest] = result as u32;
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}
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}
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Inst::Andi { imm, dest, src1 } => {
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Inst::Andi { imm, dest, src1 } => {
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@ -377,7 +374,7 @@ impl Emulator {
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}
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}
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Inst::Mulhsu { .. } => todo!("mulhsu"),
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Inst::Mulhsu { .. } => todo!("mulhsu"),
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Inst::Mulhu { dest, src1, src2 } => {
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Inst::Mulhu { dest, src1, src2 } => {
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let shifted = ((self[src1] as u64).wrapping_mul(self[src2] as u64) as u64) >> 32;
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let shifted = ((self[src1] as u64).wrapping_mul(self[src2] as u64)) >> 32;
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self[dest] = shifted as u32;
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self[dest] = shifted as u32;
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}
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}
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Inst::Div { dest, src1, src2 } => {
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Inst::Div { dest, src1, src2 } => {
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15
src/inst.rs
15
src/inst.rs
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@ -396,12 +396,11 @@ impl Display for AmoOp {
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fn sign_extend(value: u32, size: u32) -> u32 {
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fn sign_extend(value: u32, size: u32) -> u32 {
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assert!(size <= u32::BITS);
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assert!(size <= u32::BITS);
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let sign = value >> (size - 1);
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let sign = value >> (size - 1);
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let imm = if sign == 1 {
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if sign == 1 {
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(u32::MAX << size) | value
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(u32::MAX << size) | value
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} else {
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} else {
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value
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value
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};
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}
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imm
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}
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}
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#[derive(Clone, Copy)]
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#[derive(Clone, Copy)]
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@ -487,7 +486,7 @@ impl InstCodeC {
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let value = self.extract(from.clone());
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let value = self.extract(from.clone());
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imm |= value << to;
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imm |= value << to;
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}
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}
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imm as u32
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imm
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}
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}
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fn immediate_s(self, mappings: &[(RangeInclusive<u32>, u32)]) -> u32 {
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fn immediate_s(self, mappings: &[(RangeInclusive<u32>, u32)]) -> u32 {
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let mut imm = 0;
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let mut imm = 0;
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@ -512,23 +511,23 @@ impl InstCodeC {
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}
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}
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/// rd/rs1 (7..=11)
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/// rd/rs1 (7..=11)
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fn rd(self) -> Reg {
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fn rd(self) -> Reg {
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Reg(self.extract(7..=11) as u32)
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Reg(self.extract(7..=11))
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}
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}
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/// rs2 (2..=6)
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/// rs2 (2..=6)
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fn rs2(self) -> Reg {
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fn rs2(self) -> Reg {
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Reg(self.extract(2..=6) as u32)
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Reg(self.extract(2..=6))
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}
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}
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/// rs1' (7..=9)
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/// rs1' (7..=9)
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fn rs1_short(self) -> Reg {
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fn rs1_short(self) -> Reg {
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let smol_reg = self.extract(7..=9);
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let smol_reg = self.extract(7..=9);
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// map to x8..=x15
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// map to x8..=x15
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Reg(smol_reg as u32 + 8)
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Reg(smol_reg + 8)
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}
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}
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/// rs2' (2..=4)
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/// rs2' (2..=4)
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fn rs2_short(self) -> Reg {
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fn rs2_short(self) -> Reg {
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let smol_reg = self.extract(2..=4);
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let smol_reg = self.extract(2..=4);
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// map to x8..=x15
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// map to x8..=x15
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Reg(smol_reg as u32 + 8)
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Reg(smol_reg + 8)
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}
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}
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}
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}
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