slightly clean up the code

This commit is contained in:
nora 2025-03-10 20:26:49 +01:00
parent ae29dd0505
commit 13aec667db
4 changed files with 29 additions and 29 deletions

View file

@ -16,3 +16,7 @@ tempfile = "3.18.0"
[lints.rust] [lints.rust]
unexpected_cfgs = { level = "warn", check-cfg = ['cfg(slow_tests)'] } unexpected_cfgs = { level = "warn", check-cfg = ['cfg(slow_tests)'] }
[lints.clippy]
type_complexity = "allow"
if_same_then_else = "allow"

View file

@ -30,7 +30,7 @@ pub struct Phdr {
pub p_align: u32, pub p_align: u32,
} }
impl<'a> Elf<'a> { impl Elf<'_> {
pub fn header(&self) -> Result<Header> { pub fn header(&self) -> Result<Header> {
let (ident, rest) = self.content.split_bytes(16)?; let (ident, rest) = self.content.split_bytes(16)?;
if ident[..4] != *b"\x7fELF" { if ident[..4] != *b"\x7fELF" {

View file

@ -3,7 +3,6 @@ use std::{
fmt::{Debug, Display}, fmt::{Debug, Display},
io::Write, io::Write,
ops::{Index, IndexMut}, ops::{Index, IndexMut},
u32,
}; };
pub struct Memory { pub struct Memory {
@ -22,20 +21,18 @@ impl Memory {
} }
} }
pub fn slice(&self, addr: u32, len: u32) -> Result<&[u8], Status> { pub fn slice(&self, addr: u32, len: u32) -> Result<&[u8], Status> {
Ok(self self.mem
.mem
.get((addr as usize)..) .get((addr as usize)..)
.ok_or(Status::InvalidMemoryAccess(addr))? .ok_or(Status::InvalidMemoryAccess(addr))?
.get(..(len as usize)) .get(..(len as usize))
.ok_or(Status::InvalidMemoryAccess(addr))?) .ok_or(Status::InvalidMemoryAccess(addr))
} }
pub fn slice_mut(&mut self, addr: u32, len: u32) -> Result<&mut [u8], Status> { pub fn slice_mut(&mut self, addr: u32, len: u32) -> Result<&mut [u8], Status> {
Ok(self self.mem
.mem
.get_mut((addr as usize)..) .get_mut((addr as usize)..)
.ok_or(Status::InvalidMemoryAccess(addr))? .ok_or(Status::InvalidMemoryAccess(addr))?
.get_mut(..(len as usize)) .get_mut(..(len as usize))
.ok_or(Status::InvalidMemoryAccess(addr))?) .ok_or(Status::InvalidMemoryAccess(addr))
} }
pub fn load_u8(&self, addr: u32) -> Result<u8, Status> { pub fn load_u8(&self, addr: u32) -> Result<u8, Status> {
@ -48,21 +45,21 @@ impl Memory {
Ok(u32::from_le_bytes(self.slice(addr, 4)?.try_into().unwrap())) Ok(u32::from_le_bytes(self.slice(addr, 4)?.try_into().unwrap()))
} }
pub fn store_u8(&mut self, addr: u32, value: u8) -> Result<(), Status> { pub fn store_u8(&mut self, addr: u32, value: u8) -> Result<(), Status> {
Ok(self self.slice_mut(addr, 1)?
.slice_mut(addr, 1)? .copy_from_slice(&value.to_le_bytes());
.copy_from_slice(&value.to_le_bytes())) Ok(())
} }
pub fn store_u16(&mut self, addr: u32, value: u16) -> Result<(), Status> { pub fn store_u16(&mut self, addr: u32, value: u16) -> Result<(), Status> {
self.check_align(addr, 2)?; self.check_align(addr, 2)?;
Ok(self self.slice_mut(addr, 2)?
.slice_mut(addr, 2)? .copy_from_slice(&value.to_le_bytes());
.copy_from_slice(&value.to_le_bytes())) Ok(())
} }
pub fn store_u32(&mut self, addr: u32, value: u32) -> Result<(), Status> { pub fn store_u32(&mut self, addr: u32, value: u32) -> Result<(), Status> {
self.check_align(addr, 4)?; self.check_align(addr, 4)?;
Ok(self self.slice_mut(addr, 4)?
.slice_mut(addr, 4)? .copy_from_slice(&value.to_le_bytes());
.copy_from_slice(&value.to_le_bytes())) Ok(())
} }
} }
@ -313,17 +310,17 @@ impl Emulator {
} }
Inst::Sw { offset, src, base } => { Inst::Sw { offset, src, base } => {
let addr = self[base].wrapping_add(offset); let addr = self[base].wrapping_add(offset);
self.mem.store_u32(addr, self[src] as u32)?; self.mem.store_u32(addr, self[src])?;
} }
Inst::Addi { imm, dest, src1 } => { Inst::Addi { imm, dest, src1 } => {
self[dest] = self[src1].wrapping_add(imm as u32); self[dest] = self[src1].wrapping_add(imm);
} }
Inst::Slti { imm, dest, src1 } => { Inst::Slti { imm, dest, src1 } => {
let result = (self[src1] as i32) < (imm as i32); let result = (self[src1] as i32) < (imm as i32);
self[dest] = result as u32; self[dest] = result as u32;
} }
Inst::Sltiu { imm, dest, src1 } => { Inst::Sltiu { imm, dest, src1 } => {
let result = (self[src1] as u32) < imm as u32; let result = self[src1] < imm;
self[dest] = result as u32; self[dest] = result as u32;
} }
Inst::Andi { imm, dest, src1 } => { Inst::Andi { imm, dest, src1 } => {
@ -377,7 +374,7 @@ impl Emulator {
} }
Inst::Mulhsu { .. } => todo!("mulhsu"), Inst::Mulhsu { .. } => todo!("mulhsu"),
Inst::Mulhu { dest, src1, src2 } => { Inst::Mulhu { dest, src1, src2 } => {
let shifted = ((self[src1] as u64).wrapping_mul(self[src2] as u64) as u64) >> 32; let shifted = ((self[src1] as u64).wrapping_mul(self[src2] as u64)) >> 32;
self[dest] = shifted as u32; self[dest] = shifted as u32;
} }
Inst::Div { dest, src1, src2 } => { Inst::Div { dest, src1, src2 } => {

View file

@ -396,12 +396,11 @@ impl Display for AmoOp {
fn sign_extend(value: u32, size: u32) -> u32 { fn sign_extend(value: u32, size: u32) -> u32 {
assert!(size <= u32::BITS); assert!(size <= u32::BITS);
let sign = value >> (size - 1); let sign = value >> (size - 1);
let imm = if sign == 1 { if sign == 1 {
(u32::MAX << size) | value (u32::MAX << size) | value
} else { } else {
value value
}; }
imm
} }
#[derive(Clone, Copy)] #[derive(Clone, Copy)]
@ -487,7 +486,7 @@ impl InstCodeC {
let value = self.extract(from.clone()); let value = self.extract(from.clone());
imm |= value << to; imm |= value << to;
} }
imm as u32 imm
} }
fn immediate_s(self, mappings: &[(RangeInclusive<u32>, u32)]) -> u32 { fn immediate_s(self, mappings: &[(RangeInclusive<u32>, u32)]) -> u32 {
let mut imm = 0; let mut imm = 0;
@ -512,23 +511,23 @@ impl InstCodeC {
} }
/// rd/rs1 (7..=11) /// rd/rs1 (7..=11)
fn rd(self) -> Reg { fn rd(self) -> Reg {
Reg(self.extract(7..=11) as u32) Reg(self.extract(7..=11))
} }
/// rs2 (2..=6) /// rs2 (2..=6)
fn rs2(self) -> Reg { fn rs2(self) -> Reg {
Reg(self.extract(2..=6) as u32) Reg(self.extract(2..=6))
} }
/// rs1' (7..=9) /// rs1' (7..=9)
fn rs1_short(self) -> Reg { fn rs1_short(self) -> Reg {
let smol_reg = self.extract(7..=9); let smol_reg = self.extract(7..=9);
// map to x8..=x15 // map to x8..=x15
Reg(smol_reg as u32 + 8) Reg(smol_reg + 8)
} }
/// rs2' (2..=4) /// rs2' (2..=4)
fn rs2_short(self) -> Reg { fn rs2_short(self) -> Reg {
let smol_reg = self.extract(2..=4); let smol_reg = self.extract(2..=4);
// map to x8..=x15 // map to x8..=x15
Reg(smol_reg as u32 + 8) Reg(smol_reg + 8)
} }
} }