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rvdc
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8 changed files with 384 additions and 16 deletions
3
rvdc/CHANGELOG.md
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3
rvdc/CHANGELOG.md
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## 0.1.0
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Initial release.
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name = "rvdc"
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version = "0.1.0"
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description = "RISC-V instruction decoder"
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repository = "https://github.com/Noratrieb/rustv32i"
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edition = "2024"
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keywords = ["risc-v", "riscv", "decoder", "instruction", "parser"]
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categories = ["Parser implementations"]
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license = "MIT OR Apache-2.0"
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[dependencies]
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1
rvdc/LICENSE-APACHE
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1
rvdc/LICENSE-APACHE
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../LICENSE-APACHE
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1
rvdc/LICENSE-MIT
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1
rvdc/LICENSE-MIT
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../LICENSE-MIT
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189
rvdc/src/lib.rs
189
rvdc/src/lib.rs
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@ -1,36 +1,150 @@
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//! RISC-V instruction decoder.
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//!
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//! The main function is [`Inst::decode`], which will decode an instruction into the [`Inst`] enum.
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//! The [`std::fmt::Display`] impl of [`Inst`] provides disassembly functionality
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//! (note that the precise output of that implementation is not considered stable).
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//!
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//! # Register size support
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//!
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//! This crate currenly only supports RV32 instructions.
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//! RV64 instructions that are the same between versions will still be decoded successfully, but the user
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//! has to be careful around sign-extended immediates to preserve the correct value when extending them to 64 bits.
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//!
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//! RV64-specific instructions are not yet implemented, but will be in the future.
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//! The immediates will also be switched to `u64` in the future to allow for easier usage of RV64.
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//!
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//! RV128 is not intended to be supported.
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//!
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//! # Extension support
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//!
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//! The decoder currently supports the following instructions:
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//!
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//! - [x] Base RV32I instruction set
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//! - [x] M standard extension
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//! - [x] A standard extension
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//! - [x] Zalrsc standard extension
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//! - [x] Zaamo standard extension
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//! - [x] C standard extension
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//!
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//! More extensions may be implemented in the future.
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//!
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//! # Examples
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//!
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//! ```rust
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//! // Compressed addi sp, sp, -0x20
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//! // addi sp, sp, -0x20 (compressed)
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//! let x = 0x1101_u32;
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//! let expected = rvdc::Inst::Addi { imm: (-0x20_i32) as u32, dest: rvdc::Reg::SP, src1: rvdc::Reg::SP };
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//!
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//! let (inst, is_compressed) = rvdc::Inst::decode(x).unwrap();
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//! assert_eq!(inst, expected);
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//! assert_eq!(is_compressed, rvdc::IsCompressed::No);
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//! assert_eq!(is_compressed, rvdc::IsCompressed::Yes);
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//! assert_eq!(format!("{inst}"), "addi sp, sp, -32")
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//! ```
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//!
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//! ```rust
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//! // auipc t1, 0xa
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//! let x = 0x0000a317;
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//! let expected = rvdc::Inst::Auipc { uimm: 0xa << 12, dest: rvdc::Reg::T1 };
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//!
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//! let (inst, is_compressed) = rvdc::Inst::decode(x).unwrap();
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//! assert_eq!(inst, expected);
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//! assert_eq!(is_compressed, rvdc::IsCompressed::No);
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//! assert_eq!(format!("{inst}"), "auipc t1, 10")
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//! ```
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//!
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//! # Panics
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//!
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//! [`Inst::decode`] is guaranteed to **never** panic. This is ensured with a 32-bit exhaustive test.
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//!
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//! # Testing
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//!
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//! This crate is currently tested as part of an emulator, which tests many different kinds of instructions.
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//! In the future, more tests of the decoder specifically may be added.
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//!
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//! # MSRV
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//!
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//! This crate targets the latest stable as its MSRV.
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#![deny(missing_docs)]
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use std::fmt::{Debug, Display};
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use std::ops::RangeInclusive;
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/// A decoded RISC-V integer register.
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#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
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pub struct Reg(pub u32);
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pub struct Reg(pub u8);
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impl Reg {
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/// The zero register `zero` (`x0`)
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pub const ZERO: Reg = Reg(0);
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/// The return address register `ra` (`x1`)
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pub const RA: Reg = Reg(1);
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/// The stack pointer register `sp` (`x2`)
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pub const SP: Reg = Reg(2);
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// arguments, return values:
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/// The global pointer register `gp` (`x3`)
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pub const GP: Reg = Reg(3);
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/// The thread pointer register `tp` (`x4`)
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pub const TP: Reg = Reg(4);
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/// Saved register `s0` (`x8`)
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pub const S0: Reg = Reg(8);
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/// Saved register frame pointer `fp` (`s0`, `x8`)
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pub const FP: Reg = Reg(8);
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/// Saved register `s1` (`x9`)
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pub const S1: Reg = Reg(9);
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/// Saved register `s2` (`x18`)
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pub const S2: Reg = Reg(18);
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/// Saved register `s3` (`x19`)
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pub const S3: Reg = Reg(19);
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/// Saved register `s4` (`x20`)
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pub const S4: Reg = Reg(20);
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/// Saved register `s5` (`x21`)
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pub const S5: Reg = Reg(21);
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/// Saved register `s6` (`x22`)
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pub const S6: Reg = Reg(22);
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/// Saved register `s7` (`x23`)
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pub const S7: Reg = Reg(23);
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/// Saved register `s8` (`x24`)
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pub const S8: Reg = Reg(24);
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/// Saved register `s9` (`x25`)
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pub const S9: Reg = Reg(25);
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/// Saved register `s10` (`x26`)
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pub const S10: Reg = Reg(26);
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/// Saved register `s11` (`x27`)
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pub const S11: Reg = Reg(27);
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/// Argument/return value register `a0` (`x10`)
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pub const A0: Reg = Reg(10);
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/// Argument/return value register `a1` (`x11`)
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pub const A1: Reg = Reg(11);
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// arguments:
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/// Argument register `a2` (`x12`)
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pub const A2: Reg = Reg(12);
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/// Argument register `a3` (`x13`)
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pub const A3: Reg = Reg(13);
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/// Argument register `a4` (`x14`)
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pub const A4: Reg = Reg(14);
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/// Argument register `a5` (`x15`)
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pub const A5: Reg = Reg(15);
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/// Argument register `a6` (`x16`)
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pub const A6: Reg = Reg(16);
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/// Argument register `a7` (`x17`)
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pub const A7: Reg = Reg(17);
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/// Temporary register `t0` (`x5`)
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pub const T0: Reg = Reg(5);
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/// Temporary register `t1` (`x6`)
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pub const T1: Reg = Reg(6);
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/// Temporary register `t2` (`x7`)
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pub const T2: Reg = Reg(7);
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/// Temporary register `t3` (`x28`)
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pub const T3: Reg = Reg(28);
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/// Temporary register `t4` (`x29`)
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pub const T4: Reg = Reg(29);
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/// Temporary register `t5` (`x30`)
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pub const T5: Reg = Reg(30);
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/// Temporary register `t6` (`x31`)
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pub const T6: Reg = Reg(31);
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}
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impl Display for Reg {
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}
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}
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/// A RISC-V instruction.
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///
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/// Every variant is a different instruction, with immediates as `u32`.
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/// For instructions that sign-extend immediates, the immediates will have been
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/// sign-extended already, so the value can be used as-is.
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/// For instructions that have immediates in the upper bits (`lui`, `auipc`),
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/// the shift will have been done already, so the value can also be used as-is.
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#[derive(Clone, Copy, PartialEq, Eq, Hash)]
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#[rustfmt::skip]
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#[expect(missing_docs)] // enum variant fields
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pub enum Inst {
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/// Load Upper Immediate
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Lui { uimm: u32, dest: Reg },
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@ -186,16 +308,26 @@ pub enum Inst {
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},
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}
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/// The details of a RISC-V `fence` instruction.
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#[derive(Clone, Copy, PartialEq, Eq, Hash)]
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pub struct Fence {
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pub fm: u32,
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/// The `fm` field of the instruction.
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/// - `0b0000` is a normal fence
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/// - `0b1000` with `rw,rw` implies a `fence.tso`
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pub fm: u8,
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/// The predecessor set.
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pub pred: FenceSet,
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/// The sucessor set.
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pub succ: FenceSet,
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/// The `rd` field of the instruction. Currently always zero.
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pub dest: Reg,
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/// The `rs1` field of the instruction. Currently always zero.
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pub src: Reg,
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}
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/// The affected parts of a fence.
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#[derive(Clone, Copy, PartialEq, Eq, Hash)]
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#[expect(missing_docs)]
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pub struct FenceSet {
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pub device_input: bool,
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pub device_output: bool,
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/// An atomic memory operations from the Zaamo extension.
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#[derive(Clone, Copy, PartialEq, Eq, Hash)]
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pub enum AmoOp {
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/// Swap
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Swap,
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/// ADD
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Add,
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/// XOR
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Xor,
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/// AND
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And,
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/// OR
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Or,
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/// Signed minimum
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Min,
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Maxu,
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}
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/// The error used for invalid instructions containing information about the instruction and error.
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///
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/// Note that this is also returned for the defined illegal instruction of all zero.
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pub struct DecodeError {
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/// The instruction bytes that failed to decode.
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pub instruction: u32,
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}
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impl Fence {
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/// Whether this fence indicates a `pause` assembler pseudoinstruction.
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pub fn is_pause(&self) -> bool {
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self.pred
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== FenceSet {
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}
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impl AmoOrdering {
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/// Create a new [`AmoOrdering`] from the two ordering bits.
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pub fn from_aq_rl(aq: bool, rl: bool) -> Self {
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match (aq, rl) {
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(false, false) => Self::Relaxed,
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}
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/// Prints the instruction in disassembled form.
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///
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/// Note that the precise output here is not considered stable.
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impl Display for Inst {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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match *self {
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self.extract(25..=31)
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}
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fn rs1(self) -> Reg {
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Reg(self.extract(15..=19))
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Reg(self.extract(15..=19) as u8)
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}
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fn rs2(self) -> Reg {
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Reg(self.extract(20..=24))
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Reg(self.extract(20..=24) as u8)
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}
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fn rs2_imm(self) -> u32 {
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self.extract(20..=24)
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}
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fn rd(self) -> Reg {
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Reg(self.extract(7..=11))
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Reg(self.extract(7..=11) as u8)
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}
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fn imm_i(self) -> u32 {
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self.immediate_s(&[(20..=31, 0)])
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}
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/// rd/rs1 (7..=11)
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fn rd(self) -> Reg {
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Reg(self.extract(7..=11))
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Reg(self.extract(7..=11) as u8)
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}
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/// rs2 (2..=6)
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fn rs2(self) -> Reg {
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Reg(self.extract(2..=6))
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Reg(self.extract(2..=6) as u8)
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}
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/// rs1' (7..=9)
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fn rs1_short(self) -> Reg {
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let smol_reg = self.extract(7..=9);
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// map to x8..=x15
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Reg(smol_reg + 8)
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Reg((smol_reg + 8) as u8)
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}
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/// rs2' (2..=4)
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fn rs2_short(self) -> Reg {
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let smol_reg = self.extract(2..=4);
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// map to x8..=x15
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Reg(smol_reg + 8)
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Reg((smol_reg + 8) as u8)
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}
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}
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@ -621,7 +768,9 @@ impl From<InstCodeC> for InstCode {
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/// If it was not compressed, all four bytes are consumed.
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#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
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pub enum IsCompressed {
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/// Normal 4-byte instruction
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No,
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/// Compressed 2-byte instruction
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Yes,
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}
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@ -633,6 +782,7 @@ fn decode_error(instruction: impl Into<InstCode>, unexpected_field: &'static str
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}
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impl Inst {
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/// Whether the first byte of an instruction indicates a compressed or uncompressed instruction.
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pub fn first_byte_is_compressed(byte: u8) -> bool {
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(byte & 0b11) != 0b11
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}
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},
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0b101 => match code.funct7() {
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0b0000000 => Inst::Srli {
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imm: code.rs2().0,
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imm: code.rs2_imm(),
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dest: code.rd(),
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src1: code.rs1(),
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},
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0b0100000 => Inst::Srai {
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imm: code.rs2().0,
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imm: code.rs2_imm(),
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dest: code.rd(),
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src1: code.rs1(),
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},
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@ -1143,7 +1293,7 @@ impl Inst {
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match code.funct3() {
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0b000 => Inst::Fence {
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fence: Fence {
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fm,
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fm: fm as u8,
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pred,
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succ,
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dest: code.rd(),
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mod tests {
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use std::io::Write;
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use crate::Inst;
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#[test]
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#[cfg_attr(not(slow_tests), ignore)]
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fn exhaustive_decode_no_panic() {
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}
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let _ = super::Inst::decode(u32::MAX);
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}
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#[test]
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fn size_of_instruction() {
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assert!(size_of::<Inst>() <= 12);
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}
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}
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