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parent
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commit
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4 changed files with 202 additions and 116 deletions
241
rvdc/src/lib.rs
241
rvdc/src/lib.rs
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@ -102,6 +102,65 @@ impl Display for Reg {
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}
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}
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/// An immediate in an instruction.
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/// This represents the real value that will be put in the register,
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/// so sign extension has been performed if necessary, and for instructions
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/// like `lui` the value will have been shifted.
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///
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/// This type is XLEN-agnostic, use the XLEN-specific accessors to get the correct value.
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#[derive(Copy, Clone, PartialEq, Eq, Hash)]
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pub struct Imm(u32);
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impl Imm {
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/// The immediate `0`.
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/// Useful as a shortcut for `Imm::new_u32(0)` and for patterns.
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pub const ZERO: Self = Self::new_u32(0);
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/// Create a new immediate from the (if necessary) sign-extended value.
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pub const fn new_i32(value: i32) -> Self {
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Self(value as u32)
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}
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/// Create a new immediate from the (if necessary) zero-extended value.
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pub const fn new_u32(value: u32) -> Self {
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Self(value)
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}
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/// Get the `u32` (RV32) value of the immediate.
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pub const fn as_u32(self) -> u32 {
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self.0
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}
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/// Get the `i32` (RV32) value of the immediate.
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pub const fn as_i32(self) -> i32 {
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self.0 as i32
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}
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}
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impl From<i32> for Imm {
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fn from(value: i32) -> Self {
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Self::new_i32(value)
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}
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}
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impl From<u32> for Imm {
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fn from(value: u32) -> Self {
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Self::new_u32(value)
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}
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}
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impl From<Imm> for u32 {
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fn from(value: Imm) -> Self {
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value.as_u32()
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}
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}
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impl From<Imm> for i32 {
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fn from(value: Imm) -> Self {
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value.as_i32()
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}
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}
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/// A RISC-V instruction.
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///
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/// Every variant is a different instruction, with immediates as `u32`.
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@ -112,66 +171,67 @@ impl Display for Reg {
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#[derive(Clone, Copy, PartialEq, Eq, Hash)]
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#[rustfmt::skip]
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#[expect(missing_docs)] // enum variant fields
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#[non_exhaustive]
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pub enum Inst {
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/// Load Upper Immediate
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Lui { uimm: u32, dest: Reg },
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Lui { uimm: Imm, dest: Reg },
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/// Add Upper Immediate to PC
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Auipc { uimm: u32, dest: Reg },
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Auipc { uimm: Imm, dest: Reg },
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/// Jump And Link
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Jal { offset: u32, dest: Reg },
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Jal { offset: Imm, dest: Reg },
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/// Jump And Link Register (indirect)
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Jalr { offset: u32, base: Reg, dest: Reg },
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Jalr { offset: Imm, base: Reg, dest: Reg },
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/// Branch Equal
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Beq { offset: u32, src1: Reg, src2: Reg },
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Beq { offset: Imm, src1: Reg, src2: Reg },
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/// Branch Not Equal
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Bne { offset: u32, src1: Reg, src2: Reg },
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Bne { offset: Imm, src1: Reg, src2: Reg },
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/// Branch Less Than (signed)
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Blt { offset: u32, src1: Reg, src2: Reg },
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Blt { offset: Imm, src1: Reg, src2: Reg },
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/// Branch Greater or Equal (signed)
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Bge { offset: u32, src1: Reg, src2: Reg },
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Bge { offset: Imm, src1: Reg, src2: Reg },
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/// Branch Less Than Unsigned
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Bltu { offset: u32, src1: Reg, src2: Reg },
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Bltu { offset: Imm, src1: Reg, src2: Reg },
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/// Branch Greater or Equal Unsigned
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Bgeu { offset: u32, src1: Reg, src2: Reg },
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Bgeu { offset: Imm, src1: Reg, src2: Reg },
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/// Load Byte (sign-ext)
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Lb { offset: u32, dest: Reg, base: Reg },
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Lb { offset: Imm, dest: Reg, base: Reg },
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/// Load Unsigned Byte (zero-ext)
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Lbu { offset: u32, dest: Reg, base: Reg },
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Lbu { offset: Imm, dest: Reg, base: Reg },
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/// Load Half (sign-ext)
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Lh { offset: u32, dest: Reg, base: Reg },
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Lh { offset: Imm, dest: Reg, base: Reg },
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/// Load Unsigned Half (zero-ext)
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Lhu { offset: u32, dest: Reg, base: Reg },
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Lhu { offset: Imm, dest: Reg, base: Reg },
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/// Load Word
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Lw { offset: u32, dest: Reg, base: Reg },
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Lw { offset: Imm, dest: Reg, base: Reg },
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/// Store Byte
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Sb { offset: u32, src: Reg, base: Reg },
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Sb { offset: Imm, src: Reg, base: Reg },
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/// Store Half
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Sh { offset: u32, src: Reg, base: Reg },
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Sh { offset: Imm, src: Reg, base: Reg },
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/// Store Word
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Sw { offset: u32, src: Reg, base: Reg },
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Sw { offset: Imm, src: Reg, base: Reg },
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/// Add Immediate
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Addi { imm: u32, dest: Reg, src1: Reg },
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Addi { imm: Imm, dest: Reg, src1: Reg },
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/// Set Less Than Immediate (signed)
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Slti { imm: u32, dest: Reg, src1: Reg },
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Slti { imm: Imm, dest: Reg, src1: Reg },
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/// Set Less Than Immediate Unsigned
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Sltiu { imm: u32, dest: Reg, src1: Reg },
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Sltiu { imm: Imm, dest: Reg, src1: Reg },
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/// XOR Immediate
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Xori { imm: u32, dest: Reg, src1: Reg },
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Xori { imm: Imm, dest: Reg, src1: Reg },
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/// OR Immediate
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Ori { imm: u32, dest: Reg, src1: Reg },
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Ori { imm: Imm, dest: Reg, src1: Reg },
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/// AND Immediate
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Andi { imm: u32, dest: Reg, src1: Reg },
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Andi { imm: Imm, dest: Reg, src1: Reg },
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/// Shift Left Logical Immediate
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Slli { imm: u32, dest: Reg, src1: Reg },
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Slli { imm: Imm, dest: Reg, src1: Reg },
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/// Shift Right Logical Immediate (unsigned)
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Srli { imm: u32, dest: Reg, src1: Reg },
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Srli { imm: Imm, dest: Reg, src1: Reg },
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/// Shift Right Arithmetic Immediate (signed)
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Srai { imm: u32, dest: Reg, src1: Reg },
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Srai { imm: Imm, dest: Reg, src1: Reg },
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/// Add
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Add { dest: Reg, src1: Reg, src2: Reg },
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@ -385,91 +445,103 @@ impl Debug for Inst {
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impl Display for Inst {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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match *self {
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Inst::Lui { uimm, dest } => write!(f, "lui {dest}, {}", uimm >> 12),
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Inst::Auipc { uimm, dest } => write!(f, "auipc {dest}, {}", uimm >> 12),
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Inst::Lui { uimm, dest } => write!(f, "lui {dest}, {}", uimm.as_u32() >> 12),
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Inst::Auipc { uimm, dest } => write!(f, "auipc {dest}, {}", uimm.as_u32() >> 12),
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Inst::Jal { offset, dest } => {
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if dest.0 == 0 {
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write!(f, "j {}", offset as i32)
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write!(f, "j {}", offset.as_i32())
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} else {
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write!(f, "jal {dest}, {}", offset as i32)
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write!(f, "jal {dest}, {}", offset.as_i32())
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}
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}
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Inst::Jalr { offset, base, dest } => {
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if dest == Reg::ZERO && offset == 0 && base == Reg::RA {
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if dest == Reg::ZERO && offset.as_u32() == 0 && base == Reg::RA {
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write!(f, "ret")
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} else {
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write!(f, "jalr {dest}, {}({base})", offset as i32)
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write!(f, "jalr {dest}, {}({base})", offset.as_i32())
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}
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}
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Inst::Beq { offset, src1, src2 } => write!(f, "beq {src1}, {src2}, {}", offset as i32),
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Inst::Bne { offset, src1, src2 } => write!(f, "bne {src1}, {src2}, {}", offset as i32),
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Inst::Blt { offset, src1, src2 } => write!(f, "blt {src1}, {src2}, {}", offset as i32),
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Inst::Bge { offset, src1, src2 } => write!(f, "bge {src1}, {src2}, {}", offset as i32),
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Inst::Beq { offset, src1, src2 } => {
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write!(f, "beq {src1}, {src2}, {}", offset.as_i32())
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}
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Inst::Bne { offset, src1, src2 } => {
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write!(f, "bne {src1}, {src2}, {}", offset.as_i32())
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}
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Inst::Blt { offset, src1, src2 } => {
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write!(f, "blt {src1}, {src2}, {}", offset.as_i32())
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}
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Inst::Bge { offset, src1, src2 } => {
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write!(f, "bge {src1}, {src2}, {}", offset.as_i32())
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}
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Inst::Bltu { offset, src1, src2 } => {
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write!(f, "bltu {src1}, {src2}, {}", offset as i32)
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write!(f, "bltu {src1}, {src2}, {}", offset.as_i32())
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}
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Inst::Bgeu { offset, src1, src2 } => {
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write!(f, "bgeu {src1}, {src2}, {}", offset as i32)
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write!(f, "bgeu {src1}, {src2}, {}", offset.as_i32())
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}
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Inst::Lb { offset, dest, base } => write!(f, "lb {dest}, {}({base})", offset as i32),
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Inst::Lbu { offset, dest, base } => write!(f, "lbu {dest}, {}({base})", offset as i32),
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Inst::Lh { offset, dest, base } => write!(f, "lh {dest}, {}({base})", offset as i32),
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Inst::Lhu { offset, dest, base } => write!(f, "lhu {dest}, {}({base})", offset as i32),
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Inst::Lw { offset, dest, base } => write!(f, "lw {dest}, {}({base})", offset as i32),
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Inst::Sb { offset, src, base } => write!(f, "sb {src}, {}({base})", offset as i32),
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Inst::Sh { offset, src, base } => write!(f, "sh {src}, {}({base})", offset as i32),
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Inst::Sw { offset, src, base } => write!(f, "sw {src}, {}({base})", offset as i32),
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Inst::Lb { offset, dest, base } => write!(f, "lb {dest}, {}({base})", offset.as_i32()),
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Inst::Lbu { offset, dest, base } => {
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write!(f, "lbu {dest}, {}({base})", offset.as_i32())
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}
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Inst::Lh { offset, dest, base } => write!(f, "lh {dest}, {}({base})", offset.as_i32()),
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Inst::Lhu { offset, dest, base } => {
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write!(f, "lhu {dest}, {}({base})", offset.as_i32())
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}
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Inst::Lw { offset, dest, base } => write!(f, "lw {dest}, {}({base})", offset.as_i32()),
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Inst::Sb { offset, src, base } => write!(f, "sb {src}, {}({base})", offset.as_i32()),
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Inst::Sh { offset, src, base } => write!(f, "sh {src}, {}({base})", offset.as_i32()),
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Inst::Sw { offset, src, base } => write!(f, "sw {src}, {}({base})", offset.as_i32()),
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Inst::Addi { imm, dest, src1 } => {
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if dest.0 == 0 && src1.0 == 0 && imm == 0 {
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if dest.0 == 0 && src1.0 == 0 && imm.as_u32() == 0 {
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write!(f, "nop")
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} else if src1.0 == 0 {
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write!(f, "li {dest}, {}", imm as i32)
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} else if imm == 0 {
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write!(f, "li {dest}, {}", imm.as_i32())
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} else if imm.as_u32() == 0 {
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write!(f, "mv {dest}, {src1}")
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} else {
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write!(f, "addi {dest}, {src1}, {}", imm as i32)
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write!(f, "addi {dest}, {src1}, {}", imm.as_i32())
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}
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}
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Inst::Slti {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "slti {dest}, {rs1}, {}", imm as i32),
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} => write!(f, "slti {dest}, {rs1}, {}", imm.as_i32()),
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Inst::Sltiu {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "sltiu {dest}, {rs1}, {}", imm as i32),
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} => write!(f, "sltiu {dest}, {rs1}, {}", imm.as_i32()),
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Inst::Andi {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "andi {dest}, {rs1}, {}", imm as i32),
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} => write!(f, "andi {dest}, {rs1}, {}", imm.as_i32()),
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Inst::Ori {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "ori {dest}, {rs1}, {}", imm as i32),
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} => write!(f, "ori {dest}, {rs1}, {}", imm.as_i32()),
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Inst::Xori {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "xori {dest}, {rs1}, {}", imm as i32),
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} => write!(f, "xori {dest}, {rs1}, {}", imm.as_i32()),
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Inst::Slli {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "slli {dest}, {rs1}, {}", imm as i32),
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} => write!(f, "slli {dest}, {rs1}, {}", imm.as_i32()),
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Inst::Srli {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "srli {dest}, {rs1}, {}", imm as i32),
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} => write!(f, "srli {dest}, {rs1}, {}", imm.as_i32()),
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Inst::Srai {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "srai {dest}, {rs1}, {}", imm as i32),
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} => write!(f, "srai {dest}, {rs1}, {}", imm.as_i32()),
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Inst::Add { dest, src1, src2 } => {
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write!(f, "add {dest}, {src1}, {src2}")
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}
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@ -604,15 +676,15 @@ impl InstCode {
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let end_span = 32 - (range.end() + 1);
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(self.0 << (end_span)) >> (end_span + range.start())
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}
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fn immediate_u(self, mappings: &[(RangeInclusive<u32>, u32)]) -> u32 {
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fn immediate_u(self, mappings: &[(RangeInclusive<u32>, u32)]) -> Imm {
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let mut imm = 0;
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for (from, to) in mappings {
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let value = self.extract(from.clone());
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imm |= value << to;
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}
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imm
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Imm::new_u32(imm)
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}
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fn immediate_s(self, mappings: &[(RangeInclusive<u32>, u32)]) -> u32 {
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fn immediate_s(self, mappings: &[(RangeInclusive<u32>, u32)]) -> Imm {
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let mut imm = 0;
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let mut size = 0;
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for (from, to) in mappings {
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@ -621,7 +693,7 @@ impl InstCode {
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let this_size = from.end() - from.start() + 1;
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size = size.max(*to + this_size);
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}
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sign_extend(imm, size)
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Imm::new_i32(sign_extend(imm, size) as i32)
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}
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fn opcode(self) -> u32 {
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@ -645,19 +717,19 @@ impl InstCode {
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fn rd(self) -> Reg {
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Reg(self.extract(7..=11) as u8)
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}
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fn imm_i(self) -> u32 {
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fn imm_i(self) -> Imm {
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self.immediate_s(&[(20..=31, 0)])
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}
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fn imm_s(self) -> u32 {
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fn imm_s(self) -> Imm {
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self.immediate_s(&[(25..=31, 5), (7..=11, 0)])
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}
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fn imm_b(self) -> u32 {
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fn imm_b(self) -> Imm {
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self.immediate_s(&[(31..=31, 12), (7..=7, 11), (25..=30, 5), (8..=11, 1)])
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}
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fn imm_u(self) -> u32 {
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fn imm_u(self) -> Imm {
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self.immediate_u(&[(12..=31, 12)])
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}
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fn imm_j(self) -> u32 {
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fn imm_j(self) -> Imm {
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self.immediate_s(&[(31..=31, 20), (21..=30, 1), (20..=20, 11), (12..=19, 12)])
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}
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}
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@ -670,15 +742,15 @@ impl InstCodeC {
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let end_span = u16::BITS - (range.end() + 1);
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((self.0 << (end_span)) >> (end_span + range.start())) as u32
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}
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fn immediate_u(self, mappings: &[(RangeInclusive<u32>, u32)]) -> u32 {
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fn immediate_u(self, mappings: &[(RangeInclusive<u32>, u32)]) -> Imm {
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let mut imm = 0;
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for (from, to) in mappings {
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let value = self.extract(from.clone());
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imm |= value << to;
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}
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imm
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Imm::new_u32(imm)
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}
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fn immediate_s(self, mappings: &[(RangeInclusive<u32>, u32)]) -> u32 {
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fn immediate_s(self, mappings: &[(RangeInclusive<u32>, u32)]) -> Imm {
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let mut imm = 0;
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let mut size = 0;
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for (from, to) in mappings {
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@ -688,7 +760,7 @@ impl InstCodeC {
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let this_size = from.end() - from.start() + 1;
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size = size.max(*to + this_size);
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}
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sign_extend(imm, size)
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Imm::new_i32(sign_extend(imm, size) as i32)
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}
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fn quadrant(self) -> u16 {
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self.0 & 0b11
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@ -790,7 +862,7 @@ impl Inst {
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/// ```rust
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/// // Compressed addi sp, sp, -0x20
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/// let x = 0x1101_u16;
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/// let expected = rvdc::Inst::Addi { imm: (-0x20_i32) as u32, dest: rvdc::Reg::SP, src1: rvdc::Reg::SP };
|
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/// let expected = rvdc::Inst::Addi { imm: rvdc::Imm::new_i32(-0x20), dest: rvdc::Reg::SP, src1: rvdc::Reg::SP };
|
||||
///
|
||||
/// let inst = rvdc::Inst::decode_compressed(x).unwrap();
|
||||
/// assert_eq!(inst, expected);
|
||||
|
|
@ -807,7 +879,7 @@ impl Inst {
|
|||
0b000 => {
|
||||
let imm =
|
||||
code.immediate_u(&[(5..=5, 3), (6..=6, 2), (7..=10, 6), (11..=12, 4)]);
|
||||
if imm == 0 {
|
||||
if imm.as_u32() == 0 {
|
||||
return Err(decode_error(code, "uimm=0 for C.ADDISPN is reserved"));
|
||||
}
|
||||
Inst::Addi {
|
||||
|
|
@ -959,7 +1031,7 @@ impl Inst {
|
|||
// C.LUI -> lui \rd, \imm
|
||||
_ => {
|
||||
let uimm = code.immediate_s(&[(2..=6, 12), (12..=12, 17)]);
|
||||
if uimm == 0 {
|
||||
if uimm.as_u32() == 0 {
|
||||
return Err(decode_error(code, "imm"));
|
||||
}
|
||||
Inst::Lui {
|
||||
|
|
@ -1032,7 +1104,7 @@ impl Inst {
|
|||
return Err(decode_error(code, "rs1"));
|
||||
}
|
||||
Inst::Jalr {
|
||||
offset: 0,
|
||||
offset: Imm::ZERO,
|
||||
base: rd_rs1,
|
||||
dest: Reg::ZERO,
|
||||
}
|
||||
|
|
@ -1047,7 +1119,7 @@ impl Inst {
|
|||
(1, 0, 0) => Inst::Ebreak,
|
||||
// C.JALR -> jalr ra, 0(\rs1)
|
||||
(1, _, 0) if rd_rs1.0 != 0 => Inst::Jalr {
|
||||
offset: 0,
|
||||
offset: Imm::ZERO,
|
||||
base: rd_rs1,
|
||||
dest: Reg::RA,
|
||||
},
|
||||
|
|
@ -1227,12 +1299,12 @@ impl Inst {
|
|||
}
|
||||
0b101 => match code.funct7() {
|
||||
0b0000000 => Inst::Srli {
|
||||
imm: code.rs2_imm(),
|
||||
imm: Imm::new_u32(code.rs2_imm()),
|
||||
dest: code.rd(),
|
||||
src1: code.rs1(),
|
||||
},
|
||||
0b0100000 => Inst::Srai {
|
||||
imm: code.rs2_imm(),
|
||||
imm: Imm::new_u32(code.rs2_imm()),
|
||||
dest: code.rd(),
|
||||
src1: code.rs1(),
|
||||
},
|
||||
|
|
@ -1309,7 +1381,7 @@ impl Inst {
|
|||
if code.rs1().0 != 0 {
|
||||
return Err(decode_error(code, "rs1"));
|
||||
}
|
||||
match code.imm_i() {
|
||||
match code.imm_i().as_u32() {
|
||||
0b000000000000 => Inst::Ecall,
|
||||
0b000000000001 => Inst::Ebreak,
|
||||
_ => return Err(decode_error(code, "imm")),
|
||||
|
|
@ -1390,6 +1462,7 @@ mod tests {
|
|||
|
||||
use crate::Fence;
|
||||
use crate::FenceSet;
|
||||
use crate::Imm;
|
||||
use crate::Inst;
|
||||
use crate::Reg;
|
||||
|
||||
|
|
@ -1467,7 +1540,7 @@ mod tests {
|
|||
dest: Reg::ZERO, ..
|
||||
} => false,
|
||||
// This does roundtrip, but only through C.MV, not C.ADDI
|
||||
Inst::Addi { imm: 0, .. } => false,
|
||||
Inst::Addi { imm: Imm::ZERO, .. } => false,
|
||||
// This does rountrip, but not through C.ADDI
|
||||
Inst::Addi {
|
||||
dest: Reg::SP,
|
||||
|
|
@ -1478,15 +1551,15 @@ mod tests {
|
|||
Inst::Slli {
|
||||
dest: Reg::ZERO, ..
|
||||
}
|
||||
| Inst::Slli { imm: 0, .. }
|
||||
| Inst::Slli { imm: Imm::ZERO, .. }
|
||||
| Inst::Srli {
|
||||
dest: Reg::ZERO, ..
|
||||
}
|
||||
| Inst::Srli { imm: 0, .. }
|
||||
| Inst::Srli { imm: Imm::ZERO, .. }
|
||||
| Inst::Srai {
|
||||
dest: Reg::ZERO, ..
|
||||
}
|
||||
| Inst::Srai { imm: 0, .. } => false,
|
||||
| Inst::Srai { imm: Imm::ZERO, .. } => false,
|
||||
// HINT
|
||||
Inst::Lui {
|
||||
dest: Reg::ZERO, ..
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue