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atomic tests

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nora 2025-03-09 20:55:16 +01:00
parent 023d1645cd
commit 9ad5785106
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67
tests/check/zaamo.S Normal file
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# Atomic Memory Operations
#include "../helper.S"
.macro CASE_BASE inst reg mem expected_mem
li t0, 0
li t1, \mem
sw t1, (t0)
li t3, \reg
\inst t2, t3, (t0)
ASSERT_EQ t2, \mem
lw t3, (t0)
ASSERT_EQ t3, \expected_mem
.endm
.macro CASE inst reg mem expected_mem
CASE_BASE \inst, \reg, \mem, \expected_mem
CASE_BASE \inst\().aq, \reg, \mem, \expected_mem
CASE_BASE \inst\().rl, \reg, \mem, \expected_mem
CASE_BASE \inst\().aqrl, \reg, \mem, \expected_mem
.endm
START_TEST
CASE amoswap.w, 1, 0, 1
CASE amoswap.w, 10, -1, 10
CASE amoswap.w 0, 0, 0
CASE amoadd.w, 1, 1, 2
CASE amoadd.w, -1, 1, 0
CASE amoadd.w, 10, -2, 8
CASE amoand.w, 0b11, 0b11, 0b11
CASE amoand.w, -1, -1, -1
CASE amoand.w, -1, 0, 0
CASE amoand.w, -1, 40, 40
CASE amoand.w, 0b101, 0b100, 0b100
CASE amoor.w, -1, 0, -1
CASE amoor.w, -1, 40, -1
CASE amoor.w, 0, 0, 0
CASE amoor.w, 0b101, 0b110, 0b111
CASE amoxor.w, -1, 0, -1
CASE amoxor.w, -1, -1, 0
CASE amoxor.w, 0b101, 0b100, 0b001
CASE amomax.w, 0, 0, 0
CASE amomax.w, 0, 1, 1
CASE amomax.w, -1, 0, 0
CASE amomax.w 100, -100, 100
CASE amomaxu.w, 0, 0, 0
CASE amomaxu.w, 0, 1, 1
CASE amomaxu.w, -1, 0, -1
CASE amomaxu.w 100, -100, -100
CASE amomin.w, 0, 0, 0
CASE amomin.w, 0, 1, 0
CASE amomin.w, -1, 0, -1
CASE amomin.w 100, -100, -100
CASE amominu.w, 0, 0, 0
CASE amominu.w, 0, 1, 0
CASE amominu.w, -1, 0, 0
CASE amominu.w 100, -100, 100
PASS

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tests/check/zalrsc.S Normal file
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# Load-Reserved/Store-Conditional Instructions
#include "../helper.S"
.macro RESET_MEM
li t0, 0
sc.w zero, t0, (t0) # reset reservation set
li t1, -1
sw t1, 0(t0)
li t1, -2
sw t1, 4(t0)
.endm
START_TEST
RESET_MEM
lr.w t1, (t0)
ASSERT_EQ t1, -1
lr.w.aq t1, (t0)
ASSERT_EQ t1, -1
lr.w.rl t1, (t0)
ASSERT_EQ t1, -1
lr.w.aqrl t1, (t0)
ASSERT_EQ t1, -1
RESET_MEM
# invalid SC
li t2, 10
sc.w t1, t2, (t0)
ASSERT_EQ t1, 1
li t2, 10
sc.w.aq t1, t2, (t0)
ASSERT_EQ t1, 1
li t2, 10
sc.w.rl t1, t2, (t0)
ASSERT_EQ t1, 1
li t2, 10
sc.w.aqrl t1, t2, (t0)
ASSERT_EQ t1, 1
RESET_MEM
li t1, 10
lr.w zero, (t0)
sc.w t1, t1, (t0)
ASSERT_EQ t1, 0
li t1, 10
lr.w.aq zero, (t0)
sc.w.rl t1, t1, (t0)
ASSERT_EQ t1, 0
li t1, 10
lr.w.aqrl zero, (t0)
sc.w.aqrl t1, t1, (t0)
ASSERT_EQ t1, 0
PASS