atomic tests

src/inst.rs

@@ -145,8 +145,8 @@ impl Fence {
 }
 
 impl AmoOrdering {
-    pub fn from_ac_rl(ac: bool, rl: bool) -> Self {
+    pub fn from_aq_rl(aq: bool, rl: bool) -> Self {
-        match (ac, rl) {
+        match (aq, rl) {
             (false, false) => Self::Relaxed,
             (true, false) => Self::Acquire,
             (false, true) => Self::Release,
@@ -314,9 +314,9 @@ impl Display for AmoOrdering {
     fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
         match self {
             AmoOrdering::Relaxed => write!(f, ""),
-            AmoOrdering::Acquire => write!(f, ".ac"),
+            AmoOrdering::Acquire => write!(f, ".aq"),
             AmoOrdering::Release => write!(f, ".rl"),
-            AmoOrdering::SeqCst => write!(f, ".acrl"),
+            AmoOrdering::SeqCst => write!(f, ".aqrl"),
         }
     }
 }
@@ -650,17 +650,17 @@ impl Inst {
                 }
             }
             // AMO
-            00101111 => {
+            0b00101111 => {
                 // width must be W
                 if code.funct3() != 0b010 {
                     return Err(Status::IllegalInstruction(code, "funct3"));
                 }
 
                 let kind = code.extract(27..=31);
-                let ac = code.extract(26..=26) == 1;
+                let aq = code.extract(26..=26) == 1;
                 let rl = code.extract(25..=25) == 1;
 
-                let order = AmoOrdering::from_ac_rl(ac, rl);
+                let order = AmoOrdering::from_aq_rl(aq, rl);
 
                 match kind {
                     // LR

tests/check/zaamo.S

@@ -0,0 +1,67 @@
+# Atomic Memory Operations
+
+#include "../helper.S"
+
+.macro CASE_BASE inst reg mem expected_mem
+    li t0, 0
+    li t1, \mem
+    sw t1, (t0)
+    li t3, \reg
+    \inst t2, t3, (t0)
+    ASSERT_EQ t2, \mem
+    lw t3, (t0)
+    ASSERT_EQ t3, \expected_mem
+.endm
+
+.macro CASE inst reg mem expected_mem
+    CASE_BASE \inst, \reg, \mem, \expected_mem
+    CASE_BASE \inst\().aq, \reg, \mem, \expected_mem
+    CASE_BASE \inst\().rl, \reg, \mem, \expected_mem
+    CASE_BASE \inst\().aqrl, \reg, \mem, \expected_mem
+.endm
+
+START_TEST
+    CASE amoswap.w, 1, 0, 1
+    CASE amoswap.w, 10, -1, 10
+    CASE amoswap.w 0, 0, 0
+
+    CASE amoadd.w, 1, 1, 2
+    CASE amoadd.w, -1, 1, 0
+    CASE amoadd.w, 10, -2, 8
+
+    CASE amoand.w, 0b11, 0b11, 0b11
+    CASE amoand.w, -1, -1, -1
+    CASE amoand.w, -1, 0, 0
+    CASE amoand.w, -1, 40, 40
+    CASE amoand.w, 0b101, 0b100, 0b100
+
+    CASE amoor.w, -1, 0, -1
+    CASE amoor.w, -1, 40, -1
+    CASE amoor.w, 0, 0, 0
+    CASE amoor.w, 0b101, 0b110, 0b111
+
+    CASE amoxor.w, -1, 0, -1
+    CASE amoxor.w, -1, -1, 0
+    CASE amoxor.w, 0b101, 0b100, 0b001
+
+    CASE amomax.w, 0, 0, 0
+    CASE amomax.w, 0, 1, 1
+    CASE amomax.w, -1, 0, 0
+    CASE amomax.w 100, -100, 100
+
+    CASE amomaxu.w, 0, 0, 0
+    CASE amomaxu.w, 0, 1, 1
+    CASE amomaxu.w, -1, 0, -1
+    CASE amomaxu.w 100, -100, -100
+
+    CASE amomin.w, 0, 0, 0
+    CASE amomin.w, 0, 1, 0
+    CASE amomin.w, -1, 0, -1
+    CASE amomin.w 100, -100, -100
+
+    CASE amominu.w, 0, 0, 0
+    CASE amominu.w, 0, 1, 0
+    CASE amominu.w, -1, 0, 0
+    CASE amominu.w 100, -100, 100
+
+    PASS

tests/check/zalrsc.S

@@ -0,0 +1,59 @@
+# Load-Reserved/Store-Conditional Instructions
+
+#include "../helper.S"
+
+.macro RESET_MEM
+    li t0, 0
+    sc.w zero, t0, (t0) # reset reservation set
+    li t1, -1
+    sw t1, 0(t0)
+    li t1, -2
+    sw t1, 4(t0)
+.endm
+
+START_TEST
+    RESET_MEM
+
+    lr.w t1, (t0)
+    ASSERT_EQ t1, -1
+    lr.w.aq t1, (t0)
+    ASSERT_EQ t1, -1
+    lr.w.rl t1, (t0)
+    ASSERT_EQ t1, -1
+    lr.w.aqrl t1, (t0)
+    ASSERT_EQ t1, -1
+
+    RESET_MEM
+
+    # invalid SC
+    li t2, 10
+    sc.w t1, t2, (t0)
+    ASSERT_EQ t1, 1
+    li t2, 10
+    sc.w.aq t1, t2, (t0)
+    ASSERT_EQ t1, 1
+    li t2, 10
+    sc.w.rl t1, t2, (t0)
+    ASSERT_EQ t1, 1
+    li t2, 10
+    sc.w.aqrl t1, t2, (t0)
+    ASSERT_EQ t1, 1
+
+    RESET_MEM
+
+    li t1, 10
+    lr.w zero, (t0)
+    sc.w t1, t1, (t0)
+    ASSERT_EQ t1, 0
+
+    li t1, 10
+    lr.w.aq zero, (t0)
+    sc.w.rl t1, t1, (t0)
+    ASSERT_EQ t1, 0
+
+    li t1, 10
+    lr.w.aqrl zero, (t0)
+    sc.w.aqrl t1, t1, (t0)
+    ASSERT_EQ t1, 0
+
+    PASS