mirror of
https://github.com/Noratrieb/rustv32i.git
synced 2026-01-14 13:25:01 +01:00
Merge e5828c4838 into 8e17992010
This commit is contained in:
gkgoat1
GitHub
commit
a8fdd6eda8
1 changed files with 404 additions and 2 deletions
406
rvdc/src/lib.rs
406
rvdc/src/lib.rs
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@ -497,6 +497,15 @@ impl AmoOrdering {
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(true, true) => Self::SeqCst,
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}
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}
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/// Undoes [`from_aq_rel`], creating two ordering bits
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pub fn aq_rl(&self) -> (bool, bool) {
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match self {
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AmoOrdering::Relaxed => (false, false),
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AmoOrdering::Acquire => (true, false),
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AmoOrdering::Release => (false, true),
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AmoOrdering::SeqCst => (true, true),
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}
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}
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}
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impl Debug for Inst {
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@ -781,6 +790,12 @@ impl InstCode {
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let end_span = 32 - (range.end() + 1);
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(self.0 << (end_span)) >> (end_span + range.start())
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}
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fn insert(self, range: RangeInclusive<u32>, data: u32) -> Self {
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let (start,end) = (*range.start(),*range.end());
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// let start = ;
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let span_item = (1 << (end - start + 1)) - 1;
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Self(self.0 & !(span_item << start) | ((data & span_item) << start))
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}
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fn immediate_s(self, mappings: &[(RangeInclusive<u32>, u32)]) -> Imm {
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let mut imm = 0;
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let mut size = 0;
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@ -792,22 +807,51 @@ impl InstCode {
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}
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Imm::new_i32(sign_extend(imm, size) as i32)
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}
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fn with_immediate_s(self, mappings: &[(RangeInclusive<u32>, u32)], data: Imm) -> Self {
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let mut size = 0;
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for (from, to) in mappings {
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let this_size = from.end() - from.start() + 1;
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size = size.max(*to + this_size);
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}
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mappings.iter().fold(self, |this, (from, to)| {
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this.insert(
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from.clone(),
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data.as_u32() >> *to,
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)
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})
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}
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fn opcode(self) -> u32 {
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self.0 & 0b1111111
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}
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fn with_opcode(self, opcode: u32) -> Self {
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let mask = 0b1111111;
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Self(self.0 & !mask | (opcode & mask))
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}
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fn funct3(self) -> u32 {
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self.extract(12..=14)
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}
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fn funct7(self) -> u32 {
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self.extract(25..=31)
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}
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fn with_funct3(self, data: u32) -> Self {
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self.insert(12..=14, data)
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}
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fn with_funct7(self, data: u32) -> Self {
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self.insert(25..=31, data)
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}
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fn rs1(self) -> Reg {
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Reg(self.extract(15..=19) as u8)
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}
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fn rs2(self) -> Reg {
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Reg(self.extract(20..=24) as u8)
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}
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fn with_rs1(self, data: Reg) -> Self {
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self.insert(15..=19, data.0 as u32)
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}
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fn with_rs2(self, data: Reg) -> Self {
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self.insert(20..=24, data.0 as u32)
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}
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fn rs2_imm(self) -> u32 {
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self.extract(20..=24)
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}
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@ -815,9 +859,19 @@ impl InstCode {
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fn rs2_imm_plus(self) -> u32 {
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self.extract(20..=25)
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}
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fn with_rs2_imm(self, data: u32) -> Self {
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self.insert(20..=24, data)
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}
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// shifts on RV64 have one extra bit
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fn with_rs2_imm_plus(self, data: u32) -> Self {
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self.insert(20..=25, data)
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}
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fn rd(self) -> Reg {
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Reg(self.extract(7..=11) as u8)
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}
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fn with_rd(self, data: Reg) -> Self {
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self.insert(7..=11, data.0 as u32)
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}
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fn imm_i(self) -> Imm {
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self.immediate_s(&[(20..=31, 0)])
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}
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@ -834,6 +888,28 @@ impl InstCode {
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fn imm_j(self) -> Imm {
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self.immediate_s(&[(31..=31, 20), (21..=30, 1), (20..=20, 11), (12..=19, 12)])
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}
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fn with_imm_i(self, data: Imm) -> Self {
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self.with_immediate_s(&[(20..=31, 0)], data)
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}
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fn with_imm_s(self, data: Imm) -> Self {
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self.with_immediate_s(&[(25..=31, 5), (7..=11, 0)], data)
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}
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fn with_imm_b(self, data: Imm) -> Self {
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self.with_immediate_s(
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&[(31..=31, 12), (7..=7, 11), (25..=30, 5), (8..=11, 1)],
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data,
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)
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}
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fn with_imm_u(self, data: Imm) -> Self {
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// Don't be fooled by the "u", LUI/AUIPC immediates are sign-extended on RV64.
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self.with_immediate_s(&[(12..=31, 12)], data)
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}
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fn with_imm_j(self, data: Imm) -> Self {
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self.with_immediate_s(
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&[(31..=31, 20), (21..=30, 1), (20..=20, 11), (12..=19, 12)],
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data,
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)
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}
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}
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#[derive(Clone, Copy)]
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@ -1697,6 +1773,308 @@ impl Inst {
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};
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Ok(inst)
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}
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/// Encode a normal (not compressed) instruction
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pub fn encode_normal(&self, xlen: Xlen) -> u32 {
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let code = InstCode(0);
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macro_rules! BRANCH {
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($offset:ident, $src1:ident, $src2:ident => $a:expr) => {
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$a.with_opcode(0b1100011)
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.with_imm_b(*$offset)
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.with_rs1(*$src1)
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.with_rs2(*$src2)
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};
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}
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macro_rules! LOAD {
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($offset:ident, $src1:ident, $dest:ident => $a:expr) => {
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$a.with_opcode(0b0000011)
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.with_imm_i(*$offset)
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.with_rs1(*$src1)
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.with_rd(*$dest)
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};
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}
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macro_rules! STORE {
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($offset:ident, $src1:ident, $src2:ident => $a:expr) => {
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$a.with_opcode(0b0100011)
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.with_imm_s(*$offset)
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.with_rs1(*$src1)
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.with_rs2(*$src2)
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};
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}
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macro_rules! OP_IMM {
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($offset:ident, $src1:ident, $dest:ident => $a:expr) => {
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$a.with_opcode(0b0010011)
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.with_imm_i(*$offset)
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.with_rs1(*$src1)
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.with_rd(*$dest)
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};
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}
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macro_rules! OP_IMM_32 {
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($offset:ident, $src1:ident, $dest:ident => $a:expr) => {
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$a.with_opcode(0b0011011)
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.with_imm_i(*$offset)
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.with_rs1(*$src1)
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.with_rd(*$dest)
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};
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}
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macro_rules! OP {
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($src1:ident, $src2:ident, $dest:ident => $a:expr) => {
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$a.with_opcode(0b0110011)
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.with_rs2(*$src2)
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.with_rs1(*$src1)
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.with_rd(*$dest)
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};
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}
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macro_rules! OP_32 {
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($src1:ident, $src2:ident, $dest:ident => $a:expr) => {
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$a.with_opcode(0b0111011)
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.with_rs2(*$src2)
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.with_rs1(*$src1)
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.with_rd(*$dest)
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};
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}
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let code: InstCode = match self {
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Inst::Lui { uimm, dest } => {
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code.with_opcode(0b0110111).with_rd(*dest).with_imm_u(*uimm)
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}
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Inst::Auipc { uimm, dest } => {
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code.with_opcode(0b0010111).with_rd(*dest).with_imm_u(*uimm)
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}
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Inst::Jal { offset, dest } => code
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.with_opcode(0b1101111)
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.with_imm_j(*offset)
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.with_rd(*dest),
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Inst::Jalr { offset, base, dest } => code
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.with_opcode(0b1100111)
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.with_funct3(0b000)
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.with_imm_i(*offset)
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.with_rs1(*base)
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.with_rd(*dest),
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Inst::Beq { offset, src1, src2 } => {
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BRANCH!(offset,src1,src2 => code).with_funct3(0b000)
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}
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Inst::Bne { offset, src1, src2 } => {
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BRANCH!(offset,src1,src2 => code).with_funct3(0b001)
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}
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Inst::Blt { offset, src1, src2 } => {
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BRANCH!(offset,src1,src2 => code).with_funct3(0b100)
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}
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Inst::Bge { offset, src1, src2 } => {
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BRANCH!(offset,src1,src2 => code).with_funct3(0b101)
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}
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Inst::Bltu { offset, src1, src2 } => {
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BRANCH!(offset,src1,src2 => code).with_funct3(0b110)
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}
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Inst::Bgeu { offset, src1, src2 } => {
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BRANCH!(offset,src1,src2 => code).with_funct3(0b111)
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}
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Inst::Lb { offset, dest, base } => LOAD!(offset,base,dest => code).with_funct3(0b000),
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Inst::Lbu { offset, dest, base } => LOAD!(offset,base,dest => code).with_funct3(0b100),
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Inst::Lh { offset, dest, base } => LOAD!(offset,base,dest => code).with_funct3(0b001),
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Inst::Lhu { offset, dest, base } => LOAD!(offset,base,dest => code).with_funct3(0b101),
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Inst::Lw { offset, dest, base } => LOAD!(offset,base,dest => code).with_funct3(0b010),
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Inst::Lwu { offset, dest, base } => LOAD!(offset,base,dest => code).with_funct3(0b110),
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Inst::Ld { offset, dest, base } => LOAD!(offset,base,dest => code).with_funct3(0b011),
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Inst::Sb { offset, src, base } => STORE!(offset,base,src => code).with_funct3(0b000),
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Inst::Sh { offset, src, base } => STORE!(offset,base,src => code).with_funct3(0b001),
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Inst::Sw { offset, src, base } => STORE!(offset,base,src => code).with_funct3(0b010),
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Inst::Sd { offset, src, base } => STORE!(offset,base,src => code).with_funct3(0b011),
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Inst::Addi { imm, dest, src1 } => OP_IMM!(imm,src1,dest => code).with_funct3(0b000),
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Inst::AddiW { imm, dest, src1 } => OP_IMM_32!(imm,src1,dest => code).with_funct3(0b000),
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Inst::Slti { imm, dest, src1 } => OP_IMM!(imm,src1,dest => code).with_funct3(0b010),
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Inst::Sltiu { imm, dest, src1 } => OP_IMM!(imm,src1,dest => code).with_funct3(0b011),
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Inst::Xori { imm, dest, src1 } => OP_IMM!(imm,src1,dest => code).with_funct3(0b100),
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Inst::Ori { imm, dest, src1 } => OP_IMM!(imm,src1,dest => code).with_funct3(0b110),
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Inst::Andi { imm, dest, src1 } => OP_IMM!(imm,src1,dest => code).with_funct3(0b111),
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Inst::Slli { imm, dest, src1 } => OP_IMM!(imm,src1,dest => code).with_funct3(0b001),
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Inst::SlliW { imm, dest, src1 } => OP_IMM_32!(imm,src1,dest => code).with_funct3(0b001),
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Inst::Srli { imm, dest, src1 } => {
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match OP_IMM!(imm,src1,dest => code).with_funct3(0b101) {
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x => match xlen {
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Xlen::Rv32 => x.with_funct7(0b0000000).with_rs2_imm(imm.as_u32()),
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Xlen::Rv64 => x.with_funct7(0b0000000).with_rs2_imm_plus(imm.as_u32()),
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},
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}
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}
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Inst::SrliW { imm, dest, src1 } => OP_IMM_32!(imm,src1,dest => code)
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.with_funct3(0b101)
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.with_funct7(0b0000000)
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.with_rs2_imm(imm.as_u32()),
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Inst::Srai { imm, dest, src1 } => {
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match OP_IMM!(imm,src1,dest => code).with_funct3(0b101) {
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x => match xlen {
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Xlen::Rv32 => x.with_funct7(0b0100000).with_rs2_imm(imm.as_u32()),
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Xlen::Rv64 => x.with_funct7(0b0100000).with_rs2_imm_plus(imm.as_u32()),
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},
|
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}
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}
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Inst::SraiW { imm, dest, src1 } => OP_IMM_32!(imm,src1,dest => code)
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.with_funct3(0b101)
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||||
.with_funct7(0b0100000)
|
||||
.with_rs2_imm(imm.as_u32()),
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Inst::Add { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b000)
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.with_funct7(0b0000000),
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Inst::AddW { dest, src1, src2 } => OP_32!(src1,src2,dest => code)
|
||||
.with_funct3(0b000)
|
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.with_funct7(0b0000000),
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||||
Inst::Sub { dest, src1, src2 } => OP!(src1,src2,dest => code)
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||||
.with_funct3(0b000)
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||||
.with_funct7(0b0100000),
|
||||
Inst::SubW { dest, src1, src2 } => OP_32!(src1,src2,dest => code)
|
||||
.with_funct3(0b000)
|
||||
.with_funct7(0b0100000),
|
||||
Inst::Sll { dest, src1, src2 } => OP!(src1,src2,dest => code)
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||||
.with_funct3(0b001)
|
||||
.with_funct7(0b0000000),
|
||||
Inst::SllW { dest, src1, src2 } => OP_32!(src1,src2,dest => code)
|
||||
.with_funct3(0b001)
|
||||
.with_funct7(0b0000000),
|
||||
Inst::Slt { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b010)
|
||||
.with_funct7(0b0000000),
|
||||
Inst::Sltu { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b011)
|
||||
.with_funct7(0b0000000),
|
||||
Inst::Xor { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b100)
|
||||
.with_funct7(0b0000000),
|
||||
Inst::Srl { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b101)
|
||||
.with_funct7(0b0000000),
|
||||
Inst::SrlW { dest, src1, src2 } => OP_32!(src1,src2,dest => code)
|
||||
.with_funct3(0b101)
|
||||
.with_funct7(0b0000000),
|
||||
Inst::Sra { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b101)
|
||||
.with_funct7(0b0100000),
|
||||
Inst::SraW { dest, src1, src2 } => OP_32!(src1,src2,dest => code)
|
||||
.with_funct3(0b101)
|
||||
.with_funct7(0b0100000),
|
||||
Inst::Or { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b110)
|
||||
.with_funct7(0b0000000),
|
||||
Inst::And { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b111)
|
||||
.with_funct7(0b0000000),
|
||||
Inst::Fence { fence } => match code
|
||||
.with_opcode(0b0001111)
|
||||
.insert(28..=31, fence.fm as u32)
|
||||
.with_rd(fence.dest)
|
||||
.with_rs1(fence.src)
|
||||
{
|
||||
mut v => {
|
||||
let mut i = |x, b| v = v.insert(x..=x, if b { 1 } else { 0 });
|
||||
i(27, fence.pred.device_input);
|
||||
i(26, fence.pred.device_output);
|
||||
i(25, fence.pred.memory_read);
|
||||
i(24, fence.pred.memory_write);
|
||||
i(23, fence.succ.device_input);
|
||||
i(22, fence.succ.device_output);
|
||||
i(21, fence.succ.memory_read);
|
||||
i(20, fence.succ.memory_write);
|
||||
v
|
||||
}
|
||||
},
|
||||
Inst::Ecall => code
|
||||
.with_opcode(0b1110011)
|
||||
.with_imm_i(Imm::new_u32(0b000000000000)),
|
||||
Inst::Ebreak => code
|
||||
.with_opcode(0b1110011)
|
||||
.with_imm_i(Imm::new_u32(0b000000000001)),
|
||||
Inst::Mul { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b000)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::MulW { dest, src1, src2 } => OP_32!(src1,src2,dest => code)
|
||||
.with_funct3(0b000)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::Mulh { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b001)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::Mulhsu { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b010)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::Mulhu { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b011)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::Div { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b100)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::DivW { dest, src1, src2 } => OP_32!(src1,src2,dest => code)
|
||||
.with_funct3(0b100)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::Divu { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b101)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::DivuW { dest, src1, src2 } => OP_32!(src1,src2,dest => code)
|
||||
.with_funct3(0b101)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::Rem { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b110)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::RemW { dest, src1, src2 } => OP_32!(src1,src2,dest => code)
|
||||
.with_funct3(0b110)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::Remu { dest, src1, src2 } => OP!(src1,src2,dest => code)
|
||||
.with_funct3(0b111)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::RemuW { dest, src1, src2 } => OP_32!(src1,src2,dest => code)
|
||||
.with_funct3(0b111)
|
||||
.with_funct7(0b0000001),
|
||||
Inst::LrW { order, dest, addr } => match code
|
||||
.with_opcode(0b00101111)
|
||||
.with_funct3(0b010)
|
||||
.insert(26..=26, if order.aq_rl().0 { 1 } else { 0 })
|
||||
.insert(25..=25, if order.aq_rl().1 { 1 } else { 0 })
|
||||
{
|
||||
code => code.insert(27..=31, 0b00010).with_rd(*dest).with_rs1(*addr),
|
||||
},
|
||||
Inst::ScW {
|
||||
order,
|
||||
dest,
|
||||
addr,
|
||||
src,
|
||||
} => match code
|
||||
.with_opcode(0b00101111)
|
||||
.with_funct3(0b010)
|
||||
.insert(26..=26, if order.aq_rl().0 { 1 } else { 0 })
|
||||
.insert(25..=25, if order.aq_rl().1 { 1 } else { 0 })
|
||||
{
|
||||
code => code
|
||||
.insert(27..=31, 0b00011)
|
||||
.with_rd(*dest)
|
||||
.with_rs1(*addr)
|
||||
.with_rs2(*src),
|
||||
},
|
||||
Inst::AmoW {
|
||||
order,
|
||||
op,
|
||||
dest,
|
||||
addr,
|
||||
src,
|
||||
} => match code
|
||||
.with_opcode(0b00101111)
|
||||
.with_funct3(0b010)
|
||||
.insert(26..=26, if order.aq_rl().0 { 1 } else { 0 })
|
||||
.insert(25..=25, if order.aq_rl().1 { 1 } else { 0 })
|
||||
{
|
||||
code => code.with_rd(*dest).with_rs1(*addr).with_rs2(*src).insert(
|
||||
27..=31,
|
||||
match op {
|
||||
AmoOp::Swap => 0b00001,
|
||||
AmoOp::Add => 0b00000,
|
||||
AmoOp::Xor => 0b00100,
|
||||
AmoOp::And => 0b01100,
|
||||
AmoOp::Or => 0b01000,
|
||||
AmoOp::Min => 0b10000,
|
||||
AmoOp::Max => 0b10100,
|
||||
AmoOp::Minu => 0b11000,
|
||||
AmoOp::Maxu => 0b11100,
|
||||
},
|
||||
),
|
||||
},
|
||||
};
|
||||
code.0
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
|
|
@ -1704,6 +2082,7 @@ mod tests {
|
|||
extern crate std;
|
||||
use core::sync::atomic::AtomicU32;
|
||||
use core::sync::atomic::Ordering;
|
||||
use core::u32;
|
||||
use std::prelude::rust_2024::*;
|
||||
|
||||
use std::fmt::Write as _;
|
||||
|
|
@ -1741,9 +2120,32 @@ mod tests {
|
|||
std::print!("\r{}{}", "#".repeat(done), "-".repeat(100 - done));
|
||||
std::io::stdout().flush().unwrap();
|
||||
}
|
||||
let _ = Inst::decode(i, xlen);
|
||||
let i2 = Inst::decode(i, xlen);
|
||||
if let Ok((i2, crate::IsCompressed::No)) = i2 {
|
||||
if is_inst_supposed_to_roundtrip(&i2) {
|
||||
assert_eq!(
|
||||
i2,
|
||||
Inst::decode(i2.encode_normal(xlen), xlen)
|
||||
.expect("to succeed")
|
||||
.0,
|
||||
"encoded inst different: {i2} from {i} encodes differently"
|
||||
);
|
||||
}
|
||||
}
|
||||
}
|
||||
let i2 = Inst::decode(u32::MAX, xlen);
|
||||
let i = u32::MAX;
|
||||
if let Ok((i2, crate::IsCompressed::No)) = i2 {
|
||||
if is_inst_supposed_to_roundtrip(&i2) {
|
||||
assert_eq!(
|
||||
i2,
|
||||
Inst::decode(i2.encode_normal(xlen), xlen)
|
||||
.expect("to succeed")
|
||||
.0,
|
||||
"encoded inst different: {i2} from {i} encodes differently"
|
||||
);
|
||||
}
|
||||
}
|
||||
let _ = Inst::decode(u32::MAX, xlen);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue