mirror of
https://github.com/Noratrieb/rustv32i.git
synced 2026-01-14 13:25:01 +01:00
712 lines
25 KiB
Rust
712 lines
25 KiB
Rust
use crate::emu::{Status, Reg};
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use std::fmt::{Debug, Display};
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use std::ops::RangeInclusive;
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#[derive(Clone, Copy)]
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#[rustfmt::skip]
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pub enum Inst {
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Lui { uimm: u32, dest: Reg },
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Auipc { uimm: u32, dest: Reg },
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Jal { offset: u32, dest: Reg },
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Jalr { offset: u32, base: Reg, dest: Reg },
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Beq { offset: u32, src1: Reg, src2: Reg },
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Bne { offset: u32, src1: Reg, src2: Reg },
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Blt { offset: u32, src1: Reg, src2: Reg },
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Bge { offset: u32, src1: Reg, src2: Reg },
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Bltu { offset: u32, src1: Reg, src2: Reg },
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Bgeu { offset: u32, src1: Reg, src2: Reg },
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Lb { offset: u32, dest: Reg, base: Reg },
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Lbu { offset: u32, dest: Reg, base: Reg },
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Lh { offset: u32, dest: Reg, base: Reg },
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Lhu { offset: u32, dest: Reg, base: Reg },
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Lw { offset: u32, dest: Reg, base: Reg },
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Sb { offset: u32, src: Reg, base: Reg },
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Sh { offset: u32, src: Reg, base: Reg },
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Sw { offset: u32, src: Reg, base: Reg },
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Addi { imm: u32, dest: Reg, src1: Reg },
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Slti { imm: u32, dest: Reg, src1: Reg },
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Sltiu { imm: u32, dest: Reg, src1: Reg },
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Xori { imm: u32, dest: Reg, src1: Reg },
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Ori { imm: u32, dest: Reg, src1: Reg },
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Andi { imm: u32, dest: Reg, src1: Reg },
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Slli { imm: u32, dest: Reg, src1: Reg },
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Srli { imm: u32, dest: Reg, src1: Reg },
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Srai { imm: u32, dest: Reg, src1: Reg },
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Add { dest: Reg, src1: Reg, src2: Reg },
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Sub { dest: Reg, src1: Reg, src2: Reg },
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Sll { dest: Reg, src1: Reg, src2: Reg },
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Slt { dest: Reg, src1: Reg, src2: Reg },
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Sltu { dest: Reg, src1: Reg, src2: Reg },
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Xor { dest: Reg, src1: Reg, src2: Reg },
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Srl { dest: Reg, src1: Reg, src2: Reg },
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Sra { dest: Reg, src1: Reg, src2: Reg },
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Or { dest: Reg, src1: Reg, src2: Reg },
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And { dest: Reg, src1: Reg, src2: Reg },
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Fence { fence: Fence },
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Ecall,
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Ebreak,
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// M
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Mul { dest: Reg, src1: Reg, src2: Reg },
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Mulh { dest: Reg, src1: Reg, src2: Reg },
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Mulhsu { dest: Reg, src1: Reg, src2: Reg },
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Mulhu { dest: Reg, src1: Reg, src2: Reg },
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Div { dest: Reg, src1: Reg, src2: Reg },
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Divu { dest: Reg, src1: Reg, src2: Reg },
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Rem { dest: Reg, src1: Reg, src2: Reg },
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Remu { dest: Reg, src1: Reg, src2: Reg },
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// A
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LrW {
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order: AmoOrdering,
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dest: Reg,
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addr: Reg,
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},
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ScW {
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order: AmoOrdering,
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dest: Reg,
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addr: Reg,
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src: Reg,
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},
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AmoW {
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order: AmoOrdering,
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op: AmoOp,
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dest: Reg,
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addr: Reg,
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src: Reg,
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},
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}
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#[derive(Clone, Copy)]
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pub struct Fence {
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pub fm: u32,
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pub pred: FenceSet,
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pub succ: FenceSet,
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pub dest: Reg,
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pub src: Reg,
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}
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#[derive(Clone, Copy, PartialEq, Eq)]
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pub struct FenceSet {
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pub device_input: bool,
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pub device_output: bool,
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pub memory_read: bool,
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pub memory_write: bool,
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}
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#[derive(Clone, Copy)]
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pub enum AmoOrdering {
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Relaxed,
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Acquire,
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Release,
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SeqCst,
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}
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#[derive(Clone, Copy)]
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pub enum AmoOp {
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Swap,
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Add,
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Xor,
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And,
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Or,
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Min,
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Max,
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Minu,
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Maxu,
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}
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impl Fence {
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pub fn is_pause(&self) -> bool {
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self.pred
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== FenceSet {
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device_input: false,
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device_output: false,
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memory_read: false,
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memory_write: true,
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}
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&& self.succ
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== FenceSet {
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device_input: false,
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device_output: false,
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memory_read: false,
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memory_write: false,
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}
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&& self.dest == Reg::ZERO
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&& self.src == Reg::ZERO
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}
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}
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impl AmoOrdering {
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pub fn from_ac_rl(ac: bool, rl: bool) -> Self {
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match (ac, rl) {
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(false, false) => Self::Relaxed,
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(true, false) => Self::Acquire,
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(false, true) => Self::Release,
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(true, true) => Self::SeqCst,
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}
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}
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}
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impl Debug for Inst {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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Display::fmt(&self, f)
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}
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}
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impl Display for Inst {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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match *self {
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Inst::Lui { uimm, dest } => write!(f, "lui {dest}, {}", uimm >> 12),
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Inst::Auipc { uimm, dest } => write!(f, "auipc {dest}, {}", uimm >> 12),
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Inst::Jal { offset, dest } => {
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if dest.0 == 0 {
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write!(f, "j {}", offset as i32)
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} else {
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write!(f, "jal {dest}, {}", offset as i32)
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}
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}
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Inst::Jalr { offset, base, dest } => {
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write!(f, "jalr {dest}, {}({base})", offset as i32)
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}
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Inst::Beq { offset, src1, src2 } => write!(f, "beq {src1}, {src2}, {}", offset as i32),
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Inst::Bne { offset, src1, src2 } => write!(f, "bne {src1}, {src2}, {}", offset as i32),
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Inst::Blt { offset, src1, src2 } => write!(f, "blt {src1}, {src2}, {}", offset as i32),
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Inst::Bge { offset, src1, src2 } => write!(f, "bge {src1}, {src2}, {}", offset as i32),
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Inst::Bltu { offset, src1, src2 } => {
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write!(f, "bltu {src1}, {src2}, {}", offset as i32)
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}
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Inst::Bgeu { offset, src1, src2 } => {
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write!(f, "bgeu {src1}, {src2}, {}", offset as i32)
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}
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Inst::Lb { offset, dest, base } => write!(f, "lb {dest}, {}({base})", offset as i32),
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Inst::Lbu { offset, dest, base } => write!(f, "lbu {dest}, {}({base})", offset as i32),
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Inst::Lh { offset, dest, base } => write!(f, "lh {dest}, {}({base})", offset as i32),
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Inst::Lhu { offset, dest, base } => write!(f, "lhu {dest}, {}({base})", offset as i32),
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Inst::Lw { offset, dest, base } => write!(f, "lw {dest}, {}({base})", offset as i32),
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Inst::Sb { offset, src, base } => write!(f, "sb {src}, {}({base})", offset as i32),
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Inst::Sh { offset, src, base } => write!(f, "sh {src}, {}({base})", offset as i32),
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Inst::Sw { offset, src, base } => write!(f, "sw {src}, {}({base})", offset as i32),
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Inst::Addi {
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imm,
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dest: rd,
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src1: rs1,
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} => {
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if rs1.0 == 0 {
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write!(f, "li {rd}, {}", imm as i32)
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} else if imm == 0 {
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write!(f, "mv {rd}, {rs1}")
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} else {
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write!(f, "addi {rd}, {rs1}, {}", imm as i32)
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}
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}
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Inst::Slti {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "slti {dest}, {rs1}, {}", imm as i32),
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Inst::Sltiu {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "sltiu {dest}, {rs1}, {}", imm as i32),
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Inst::Andi {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "andi {dest}, {rs1}, {}", imm as i32),
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Inst::Ori {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "ori {dest}, {rs1}, {}", imm as i32),
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Inst::Xori {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "xori {dest}, {rs1}, {}", imm as i32),
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Inst::Slli {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "slli {dest}, {rs1}, {}", imm as i32),
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Inst::Srli {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "srli {dest}, {rs1}, {}", imm as i32),
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Inst::Srai {
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imm,
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dest,
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src1: rs1,
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} => write!(f, "srai {dest}, {rs1}, {}", imm as i32),
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Inst::Add { dest, src1, src2 } => write!(f, "add {dest}, {src1}, {src2}"),
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Inst::Sub { dest, src1, src2 } => write!(f, "sub {dest}, {src1}, {src2}"),
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Inst::Sll { dest, src1, src2 } => write!(f, "sll {dest}, {src1}, {src2}"),
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Inst::Slt { dest, src1, src2 } => write!(f, "slt {dest}, {src1}, {src2}"),
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Inst::Sltu { dest, src1, src2 } => write!(f, "sltu {dest}, {src1}, {src2}"),
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Inst::Xor { dest, src1, src2 } => write!(f, "xor {dest}, {src1}, {src2}"),
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Inst::Srl { dest, src1, src2 } => write!(f, "srl {dest}, {src1}, {src2}"),
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Inst::Sra { dest, src1, src2 } => write!(f, "sra {dest}, {src1}, {src2}"),
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Inst::Or { dest, src1, src2 } => write!(f, "or {dest}, {src1}, {src2}"),
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Inst::And { dest, src1, src2 } => write!(f, "and {dest}, {src1}, {src2}"),
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Inst::Fence { fence } => match fence.fm {
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0b1000 => write!(f, "fence.TSO"),
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0b0000 if fence.is_pause() => {
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write!(f, "pause")
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}
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_ => write!(f, "fence {},{}", fence.pred, fence.succ),
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},
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Inst::Ecall => write!(f, "ecall"),
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Inst::Ebreak => write!(f, "ebreak"),
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Inst::Mul { dest, src1, src2 } => write!(f, "mul {dest}, {src1}, {src2}"),
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Inst::Mulh { dest, src1, src2 } => write!(f, "mulh {dest}, {src1}, {src2}"),
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Inst::Mulhsu { dest, src1, src2 } => write!(f, "mulhsu {dest}, {src1}, {src2}"),
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Inst::Mulhu { dest, src1, src2 } => write!(f, "mulhu {dest}, {src1}, {src2}"),
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Inst::Div { dest, src1, src2 } => write!(f, "div {dest}, {src1}, {src2}"),
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Inst::Divu { dest, src1, src2 } => write!(f, "divu {dest}, {src1}, {src2}"),
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Inst::Rem { dest, src1, src2 } => write!(f, "rem {dest}, {src1}, {src2}"),
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Inst::Remu { dest, src1, src2 } => write!(f, "remu {dest}, {src1}, {src2}"),
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Inst::LrW { order, dest, addr } => write!(f, "lr.w{order} {dest}, ({addr})",),
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Inst::ScW {
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order,
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dest,
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addr,
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src,
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} => write!(f, "sc.w{order} {dest}, {src}, ({addr})"),
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Inst::AmoW {
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order,
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op,
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dest,
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addr,
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src,
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} => write!(f, "am{op}.w{order} {dest}, {src}, ({addr})",),
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}
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}
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}
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impl Display for FenceSet {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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if self.device_input {
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write!(f, "i")?;
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}
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if self.device_output {
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write!(f, "o")?;
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}
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if self.memory_read {
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write!(f, "r")?;
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}
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if self.memory_write {
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write!(f, "w")?;
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}
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Ok(())
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}
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}
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impl Display for AmoOrdering {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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match self {
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AmoOrdering::Relaxed => write!(f, ""),
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AmoOrdering::Acquire => write!(f, ".ac"),
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AmoOrdering::Release => write!(f, ".rl"),
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AmoOrdering::SeqCst => write!(f, ".acrl"),
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}
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}
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}
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impl Display for AmoOp {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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match self {
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AmoOp::Swap => write!(f, "swap"),
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AmoOp::Add => write!(f, "add"),
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AmoOp::Xor => write!(f, "xor"),
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AmoOp::And => write!(f, "and"),
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AmoOp::Or => write!(f, "or"),
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AmoOp::Min => write!(f, "min"),
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AmoOp::Max => write!(f, "max"),
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AmoOp::Minu => write!(f, "minu"),
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AmoOp::Maxu => write!(f, "maxu"),
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}
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}
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}
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fn sign_extend(value: u32, size: u32) -> u32 {
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assert!(size <= u32::BITS);
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let sign = value >> (size - 1);
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let imm = if sign == 1 {
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(u32::MAX << size) | value
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} else {
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value
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};
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imm
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}
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#[derive(Clone, Copy)]
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pub struct InstCode(u32);
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impl InstCode {
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fn extract(self, range: RangeInclusive<u32>) -> u32 {
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let end_span = 32 - (range.end() + 1);
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(self.0 << (end_span)) >> (end_span + range.start())
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}
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fn opcode(self) -> u32 {
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self.0 & 0b1111111
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}
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fn funct3(self) -> u32 {
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self.extract(12..=14)
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}
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fn funct7(self) -> u32 {
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self.extract(25..=31)
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}
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fn rs1(self) -> Reg {
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Reg(self.extract(15..=19))
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}
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fn rs2(self) -> Reg {
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Reg(self.extract(20..=24))
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}
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fn rd(self) -> Reg {
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Reg(self.extract(7..=11))
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}
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fn imm_i(self) -> u32 {
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let imm = self.extract(20..=31);
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sign_extend(imm, 12)
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}
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fn imm_s(self) -> u32 {
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let imm_11_5 = self.extract(25..=31);
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let imm_4_0 = self.extract(7..=11);
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let imm = (imm_11_5 << 5) | imm_4_0;
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sign_extend(imm, 12)
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}
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fn imm_b(self) -> u32 {
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let imm_12 = self.extract(31..=31);
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let imm_10_5 = self.extract(25..=30);
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let imm_4_1 = self.extract(8..=11);
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let imm_11 = self.extract(7..=7);
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let imm = (imm_12 << 12) | (imm_11 << 11) | (imm_10_5 << 5) | (imm_4_1 << 1);
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sign_extend(imm, 13) // 13 due to 2-byte immediate offset
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}
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fn imm_u(self) -> u32 {
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let imm_12_31 = self.extract(12..=31);
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imm_12_31 << 12
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}
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fn imm_j(self) -> u32 {
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let imm_20 = self.extract(31..=31);
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let imm_10_1 = self.extract(21..=30);
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let imm_11 = self.extract(20..=20);
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let imm_19_12 = self.extract(12..=19);
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let imm = (imm_20 << 19) | (imm_19_12 << 11) | (imm_11 << 10) | imm_10_1;
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sign_extend(imm, 20) << 1
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}
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}
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impl Debug for InstCode {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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write!(f, "{:0>32b}", self.0)
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}
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}
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impl Inst {
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pub fn decode(code: u32) -> Result<Inst, Status> {
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let code = InstCode(code);
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let inst = match code.opcode() {
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// LUI
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0b0110111 => Inst::Lui {
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uimm: code.imm_u(),
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dest: code.rd(),
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},
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// AUIPC
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0b0010111 => Inst::Auipc {
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uimm: code.imm_u(),
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dest: code.rd(),
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},
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// JAL
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0b1101111 => Inst::Jal {
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offset: code.imm_j(),
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dest: code.rd(),
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},
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// JALR
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0b1100111 => match code.funct3() {
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0b000 => Inst::Jalr {
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offset: code.imm_i(),
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base: code.rs1(),
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dest: code.rd(),
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},
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_ => return Err(Status::IllegalInstruction(code, "funct3")),
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},
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// BRANCH
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0b1100011 => match code.funct3() {
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0b000 => Inst::Beq {
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offset: code.imm_b(),
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src1: code.rs1(),
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src2: code.rs2(),
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},
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0b001 => Inst::Bne {
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offset: code.imm_b(),
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src1: code.rs1(),
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src2: code.rs2(),
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},
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0b100 => Inst::Blt {
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offset: code.imm_b(),
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src1: code.rs1(),
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src2: code.rs2(),
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},
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|
0b101 => Inst::Bge {
|
|
offset: code.imm_b(),
|
|
src1: code.rs1(),
|
|
src2: code.rs2(),
|
|
},
|
|
0b110 => Inst::Bltu {
|
|
offset: code.imm_b(),
|
|
src1: code.rs1(),
|
|
src2: code.rs2(),
|
|
},
|
|
0b111 => Inst::Bgeu {
|
|
offset: code.imm_b(),
|
|
src1: code.rs1(),
|
|
src2: code.rs2(),
|
|
},
|
|
_ => return Err(Status::IllegalInstruction(code, "funct3")),
|
|
},
|
|
// LOAD
|
|
0b0000011 => match code.funct3() {
|
|
0b000 => Inst::Lb {
|
|
offset: code.imm_i(),
|
|
dest: code.rd(),
|
|
base: code.rs1(),
|
|
},
|
|
0b001 => Inst::Lh {
|
|
offset: code.imm_i(),
|
|
dest: code.rd(),
|
|
base: code.rs1(),
|
|
},
|
|
0b010 => Inst::Lw {
|
|
offset: code.imm_i(),
|
|
dest: code.rd(),
|
|
base: code.rs1(),
|
|
},
|
|
0b100 => Inst::Lbu {
|
|
offset: code.imm_i(),
|
|
dest: code.rd(),
|
|
base: code.rs1(),
|
|
},
|
|
0b101 => Inst::Lhu {
|
|
offset: code.imm_i(),
|
|
dest: code.rd(),
|
|
base: code.rs1(),
|
|
},
|
|
_ => return Err(Status::IllegalInstruction(code, "funct3")),
|
|
},
|
|
// STORE
|
|
0b0100011 => match code.funct3() {
|
|
0b000 => Inst::Sb {
|
|
offset: code.imm_s(),
|
|
src: code.rs2(),
|
|
base: code.rs1(),
|
|
},
|
|
0b001 => Inst::Sh {
|
|
offset: code.imm_s(),
|
|
src: code.rs2(),
|
|
base: code.rs1(),
|
|
},
|
|
0b010 => Inst::Sw {
|
|
offset: code.imm_s(),
|
|
src: code.rs2(),
|
|
base: code.rs1(),
|
|
},
|
|
_ => return Err(Status::IllegalInstruction(code, "funct3")),
|
|
},
|
|
// OP-IMM
|
|
0b0010011 => match code.funct3() {
|
|
0b000 => Inst::Addi {
|
|
imm: code.imm_i(),
|
|
dest: code.rd(),
|
|
src1: code.rs1(),
|
|
},
|
|
0b010 => Inst::Slti {
|
|
imm: code.imm_i(),
|
|
dest: code.rd(),
|
|
src1: code.rs1(),
|
|
},
|
|
0b011 => Inst::Sltiu {
|
|
imm: code.imm_i(),
|
|
dest: code.rd(),
|
|
src1: code.rs1(),
|
|
},
|
|
0b100 => Inst::Xori {
|
|
imm: code.imm_i(),
|
|
dest: code.rd(),
|
|
src1: code.rs1(),
|
|
},
|
|
0b110 => Inst::Ori {
|
|
imm: code.imm_i(),
|
|
dest: code.rd(),
|
|
src1: code.rs1(),
|
|
},
|
|
0b111 => Inst::Andi {
|
|
imm: code.imm_i(),
|
|
dest: code.rd(),
|
|
src1: code.rs1(),
|
|
},
|
|
0b001 => Inst::Slli {
|
|
imm: code.imm_i(),
|
|
dest: code.rd(),
|
|
src1: code.rs1(),
|
|
},
|
|
0b101 => match code.funct7() {
|
|
0b0000000 => Inst::Srli {
|
|
imm: code.rs2().0,
|
|
dest: code.rd(),
|
|
src1: code.rs1(),
|
|
},
|
|
0b0100000 => Inst::Srai {
|
|
imm: code.rs2().0,
|
|
dest: code.rd(),
|
|
src1: code.rs1(),
|
|
},
|
|
_ => return Err(Status::IllegalInstruction(code, "funct7")),
|
|
},
|
|
_ => return Err(Status::IllegalInstruction(code, "funct3")),
|
|
},
|
|
// OP
|
|
0b0110011 => {
|
|
let (dest, src1, src2) = (code.rd(), code.rs1(), code.rs2());
|
|
match (code.funct3(), code.funct7()) {
|
|
(0b000, 0b0000000) => Inst::Add { dest, src1, src2 },
|
|
(0b000, 0b0100000) => Inst::Sub { dest, src1, src2 },
|
|
(0b001, 0b0000000) => Inst::Sll { dest, src1, src2 },
|
|
(0b010, 0b0000000) => Inst::Slt { dest, src1, src2 },
|
|
(0b011, 0b0000000) => Inst::Sltu { dest, src1, src2 },
|
|
(0b100, 0b0000000) => Inst::Xor { dest, src1, src2 },
|
|
(0b101, 0b0000000) => Inst::Srl { dest, src1, src2 },
|
|
(0b101, 0b0100000) => Inst::Sra { dest, src1, src2 },
|
|
(0b110, 0b0000000) => Inst::Or { dest, src1, src2 },
|
|
(0b111, 0b0000000) => Inst::And { dest, src1, src2 },
|
|
|
|
(0b000, 0b0000001) => Inst::Mul { dest, src1, src2 },
|
|
(0b001, 0b0000001) => Inst::Mulh { dest, src1, src2 },
|
|
(0b010, 0b0000001) => Inst::Mulhsu { dest, src1, src2 },
|
|
(0b011, 0b0000001) => Inst::Mulhu { dest, src1, src2 },
|
|
(0b100, 0b0000001) => Inst::Div { dest, src1, src2 },
|
|
(0b101, 0b0000001) => Inst::Divu { dest, src1, src2 },
|
|
(0b110, 0b0000001) => Inst::Rem { dest, src1, src2 },
|
|
(0b111, 0b0000001) => Inst::Remu { dest, src1, src2 },
|
|
_ => return Err(Status::IllegalInstruction(code, "funct3/funct7")),
|
|
}
|
|
}
|
|
// MISC-MEM
|
|
0b0001111 => {
|
|
let fm = code.extract(28..=31);
|
|
let pred = FenceSet {
|
|
device_input: code.extract(27..=27) == 1,
|
|
device_output: code.extract(26..=26) == 1,
|
|
memory_read: code.extract(25..=25) == 1,
|
|
memory_write: code.extract(24..=24) == 1,
|
|
};
|
|
let succ = FenceSet {
|
|
device_input: code.extract(23..=23) == 1,
|
|
device_output: code.extract(22..=22) == 1,
|
|
memory_read: code.extract(21..=21) == 1,
|
|
memory_write: code.extract(20..=20) == 1,
|
|
};
|
|
|
|
match code.funct3() {
|
|
0b000 => Inst::Fence {
|
|
fence: Fence {
|
|
fm,
|
|
pred,
|
|
succ,
|
|
dest: code.rd(),
|
|
src: code.rs1(),
|
|
},
|
|
},
|
|
_ => return Err(Status::IllegalInstruction(code, "funct3")),
|
|
}
|
|
}
|
|
// SYSTEM
|
|
0b1110011 => {
|
|
if code.0 == 0b11000000000000000001000001110011 {
|
|
return Err(Status::Trap("unimp instruction"));
|
|
}
|
|
if code.rd().0 != 0 {
|
|
return Err(Status::IllegalInstruction(code, "rd"));
|
|
}
|
|
if code.funct3() != 0 {
|
|
return Err(Status::IllegalInstruction(code, "funct3"));
|
|
}
|
|
if code.rs1().0 != 0 {
|
|
return Err(Status::IllegalInstruction(code, "rs1"));
|
|
}
|
|
match code.imm_i() {
|
|
0b000000000000 => Inst::Ecall,
|
|
0b000000000001 => Inst::Ebreak,
|
|
_ => return Err(Status::IllegalInstruction(code, "imm")),
|
|
}
|
|
}
|
|
// AMO
|
|
00101111 => {
|
|
// width must be W
|
|
if code.funct3() != 0b010 {
|
|
return Err(Status::IllegalInstruction(code, "funct3"));
|
|
}
|
|
|
|
let kind = code.extract(27..=31);
|
|
let ac = code.extract(26..=26) == 1;
|
|
let rl = code.extract(25..=25) == 1;
|
|
|
|
let order = AmoOrdering::from_ac_rl(ac, rl);
|
|
|
|
match kind {
|
|
// LR
|
|
0b00010 => {
|
|
if code.rs2().0 != 0 {
|
|
return Err(Status::IllegalInstruction(code, "rs2"));
|
|
}
|
|
|
|
Inst::LrW {
|
|
order,
|
|
dest: code.rd(),
|
|
addr: code.rs1(),
|
|
}
|
|
}
|
|
// SC
|
|
0b00011 => Inst::ScW {
|
|
order,
|
|
dest: code.rd(),
|
|
addr: code.rs1(),
|
|
src: code.rs2(),
|
|
},
|
|
_ => {
|
|
let op = match kind {
|
|
0b00001 => AmoOp::Swap,
|
|
0b00000 => AmoOp::Add,
|
|
0b00100 => AmoOp::Xor,
|
|
0b01100 => AmoOp::And,
|
|
0b01000 => AmoOp::Or,
|
|
0b10000 => AmoOp::Min,
|
|
0b10100 => AmoOp::Max,
|
|
0b11000 => AmoOp::Minu,
|
|
0b11100 => AmoOp::Maxu,
|
|
_ => return Err(Status::IllegalInstruction(code, "funct7")),
|
|
};
|
|
Inst::AmoW {
|
|
order,
|
|
op,
|
|
dest: code.rd(),
|
|
addr: code.rs1(),
|
|
src: code.rs2(),
|
|
}
|
|
}
|
|
}
|
|
}
|
|
_ => return Err(Status::IllegalInstruction(code, "opcode")),
|
|
};
|
|
Ok(inst)
|
|
}
|
|
}
|