mirror of
https://github.com/Noratrieb/rustv32i.git
synced 2026-01-14 21:35:02 +01:00
172 lines
3.7 KiB
ArmAsm
172 lines
3.7 KiB
ArmAsm
# Integer computational register-register instruction.
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#include "../helper.S"
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.macro CASER inst:req a:req b:req expected:req
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li t0, \a
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li t1, \b
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\inst t2, t0, t1
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ASSERT_EQ t2, \expected
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.endm
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.macro CASE_IMM inst:req a:req b:req expected:req
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li t0, \a
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\inst t2, t0, \b
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ASSERT_EQ t2, \expected
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.endm
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.macro CASE_BOTH inst:req insti:req a:req b:req expected:req
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CASER \inst, \a, \b, \expected
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CASE_IMM \insti, \a, \b, \expected
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.endm
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.macro CASE inst:req a:req b:req expected:req
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CASE_BOTH \inst, \inst\()i, \a, \b, \expected
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.endm
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START_TEST
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# Base instructions
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.macro CASE_ADD a:req, b:req
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CASE add, \a, \b, \a + \b
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.endm
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WITH_TWO_TEST_NUMBERS CASE_ADD
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CASE slt 10 20 1
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CASE slt 20 10 0
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CASE slt, -1 0 1
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CASE slt 0, -1 0
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CASE slt, -1, -1, 0
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CASE slt, -100, -1, 1
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CASE_BOTH sltu sltiu 10 20 1
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CASE_BOTH sltu sltiu 20 10 0
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CASE_BOTH sltu sltiu, -1, 0, 0
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CASE_BOTH sltu sltiu, -100, -1, 1
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CASE_BOTH sltu sltiu, 100, -1, 1
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CASE and 0b11, 0b11, 0b11
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CASE and, -1, -1, -1
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CASE and, -1, 0, 0
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CASE and, -1, 40, 40
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CASE and, 0b101, 0b100, 0b100
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.macro CASE_AND a:req, b:req
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CASE and, \a, \b, \a & \b
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.endm
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WITH_TWO_TEST_NUMBERS CASE_AND
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CASE or, -1, 0, -1
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CASE or, -1, 40, -1
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CASE or, 0, 0, 0
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CASE or, 0b101, 0b110, 0b111
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.macro CASE_OR a:req, b:req
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CASE or, \a, \b, \a | \b
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.endm
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WITH_TWO_TEST_NUMBERS CASE_OR
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CASE xor, -1, 0, -1
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CASE xor, -1, -1, 0
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CASE xor 0b101, 0b100, 0b001
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.macro CASE_XOR a:req, b:req
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CASE xor, \a, \b, \a ^ \b
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.endm
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WITH_TWO_TEST_NUMBERS CASE_XOR
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CASE sll, 2, 1, 4
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CASE sll, 2, 20, 2097152
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CASE sll, 2, 30, 2147483648
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CASE sll, 2, 31, 0
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CASER sll, 2, 32, 2 # error for immediate
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CASE sll, 0, 10, 0
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CASE sll, 10, 0, 10
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CASE sll, -1, 31, -2147483648
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CASER sll, -1, 32, -1 # error for immediate
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CASE srl, 4, 1, 2
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CASE srl, 0, 10, 0
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CASE srl, 10, 0, 10
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CASE srl, -1, 1, 2147483647
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CASE srl, 0b111, 2, 0b001
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CASER srl, -1, 32, -1 # error for immediate
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CASER sub, 10, 5, 5
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CASER sub, -1, 1, -2
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CASER sub, 1, 2, -1
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CASER sub, -1, -2, 1
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CASER sub, 0, 4294967295, 1
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.macro CASE_SUB a:req, b:req
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CASER sub, \a, \b, \a - \b
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.endm
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WITH_TWO_TEST_NUMBERS CASE_SUB
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CASE sra, 4, 1, 2
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CASE sra, 0, 10, 0
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CASE sra, 10, 0, 10
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CASE sra, -1, 1, -1
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CASE sra, -1, 31, -1
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CASE sra, 0b111, 2, 0b001
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CASER sra, 10, 32, 10 # error for immediate
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# M extension
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CASER mul, 4, 4, 16
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CASER mul, 10, 0, 0
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CASER mul, 10, 1, 10
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CASER mul, -1, -1, 1
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CASER mul, 25252566, 5225225, 353909638
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.macro CASE_MUL a:req, b:req
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CASER mul, \a, \b, \a * \b
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.endm
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WITH_TWO_TEST_NUMBERS CASE_MUL
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CASER mulh 4, 4, 0
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CASER mulh, -1, -1, 0
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CASER mulh, 25252566, 5225225, 30722
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CASER mulhu 4, 4, 0
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CASER mulhu, -1, -1, 4294967294
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CASER mulhu, 25252566, 5225225, 30722
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# mulhsu hasn't been implemented yet.
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CASER div, 4, 2, 2
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CASER div, -1, 1, -1
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CASER div, 1, 1, 1
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CASER div, 1, 0, -1
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CASER div, -10, 2, -5
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CASER div, 5, 2, 2
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CASER div, 5, -1, -5
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CASER div, -2147483648, -1, -1
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CASER divu, 4, 2, 2
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CASER divu, -1, 1, -1
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CASER divu, 1, 1, 1
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CASER divu, 1, 0, -1
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CASER divu, -10, 2, 2147483643
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CASER divu, 5, 2, 2
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CASER rem, 4, 2, 0
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CASER rem, 5, 2, 1
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CASER rem, 5, 0, 5
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CASER rem, -10, 3, -1
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CASER rem, 5, -1, 0
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CASER rem, -2147483648, -1, 0
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CASER remu, 4, 2, 0
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CASER remu, 5, 2, 1
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CASER remu, 5, 0, 5
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CASER remu, -10, 3, 0
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PASS
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