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https://github.com/Noratrieb/uwucc.git
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do some registers
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parent
a363b7c6d1
commit
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9 changed files with 227 additions and 97 deletions
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@ -1,3 +1,4 @@
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mod registers;
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mod x86_64;
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use std::process::Stdio;
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@ -18,6 +19,13 @@ pub fn generate<'cx>(lcx: &'cx LoweringCx<'cx>, ir: &Ir<'cx>) -> Result<()> {
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object::Endianness::Little,
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);
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// GNU linkers have this awesome thing where they'll mark your stack as executable unless you tell them not to.
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obj.add_section(
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Vec::new(),
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b".note.GNU-stack".to_vec(),
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object::SectionKind::Note,
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);
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let text = obj.add_section(Vec::new(), b".text".to_vec(), object::SectionKind::Text);
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for func in ir.funcs.values() {
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122
codegen/src/registers.rs
Normal file
122
codegen/src/registers.rs
Normal file
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@ -0,0 +1,122 @@
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//! # Register allocation
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//!
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//! Register allocation is not very smart, but also not too stupid. It tries to put SSA
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//! registers into machine registers as much as possible.
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//!
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//! ```text
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//! bb0:
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//! %0 = 0
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//! %1 = 1
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//! %2 = add %0 %1
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//! switch %2, then bb1, else bb2
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//!
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//! bb1:
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//! %3 = add %1, 1
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//!
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//! bb2:
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//! %4 = add %2, 2
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//! ```
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//!
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//! For all SSA registers, we establish their "point of last use". This is the bb,stmt where their last usage occurs.
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//!
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//! First, we establish a list of possible registers to allocate.
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//! Since we immediately alloca all parameters, all the param registers are free real estate.
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//!
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//! ```text
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//! rax, rdi, rsi, rcx, rdx, r8, r9
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//! ```
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//!
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//! This forms our priority list of registers.
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//!
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//! Every time a statement has a return value, we try to assign that SSA register into a new machine register.
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//! For this, we iterate through the register list above and find the first register that's free. If we see a register
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//! that is not used anymore at the current location, we throw it out and use that new slot.
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//!
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//! When codegening an SSA register, we look into a lookup table from SSA register to machine register/stack spill and use that.
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//!
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//! When the list above is full, we spill the register to the stack. This should be rare. If the register doesn't fit into a machine
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//! register, it's also spilled.
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//!
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//! We do a first pass over the function to calculate all the offsets and registers
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//! we want to use.
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use std::cell::Cell;
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use analysis::ir::{self, Func, Location, Register};
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use rustc_hash::FxHashMap;
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/// A machine register from our register list described in the module documentation.
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#[derive(Debug, Clone, Copy)]
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pub struct MachineReg(pub usize);
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#[derive(Debug, Clone, Copy)]
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pub enum RegValue {
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/// The SSA register contains an address on the stack.
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/// The offset is the offset from the start of the function.
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StackRelative { offset: u64 },
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/// The SSA register resides on the stack as it has been spilled.
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/// This should be rather rare in practice.
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Spilled { offset: u64 },
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/// The SSA register resides in a machine register.
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MachineReg(MachineReg),
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}
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#[derive(Debug)]
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pub struct FunctionLayout {
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/// Where a register comes from at a particular usage of a register.
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register_uses: FxHashMap<(Location, Register), RegValue>,
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total_stack_space: u64,
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}
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pub fn compute_layout(f: &Func) -> FunctionLayout {
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let register_uses = FxHashMap::default();
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FunctionLayout {
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register_uses,
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total_stack_space: 0,
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}
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}
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pub struct LayoutPrinter<'a>(Cell<Option<&'a Func<'a>>>, &'a FunctionLayout);
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impl<'a> ir::pretty::Customizer<'a> for LayoutPrinter<'a> {
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fn start_func(&self, func: &'a Func<'a>) {
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self.0.set(Some(func));
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}
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fn fmt_reg(
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&self,
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reg: Register,
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f: &mut std::fmt::Formatter<'_>,
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loc: Location,
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) -> std::fmt::Result {
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let layout = self.1.register_uses.get(&(loc, reg));
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write!(f, "{{")?;
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match self.0.get().unwrap().regs[reg.0 as usize].name {
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None => write!(f, "%{}", reg.0)?,
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Some(name) => write!(f, "%{name}")?,
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}
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write!(f, ", ")?;
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match layout {
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Some(RegValue::MachineReg(mach)) => write!(f, "reg-{}", mach.0)?,
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Some(RegValue::Spilled { offset }) => write!(f, "spill-{offset}")?,
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Some(RegValue::StackRelative { offset }) => {
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write!(f, "i-forgot-what-this-meant-{offset}")?
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}
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None => write!(f, "<unknown>")?,
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}
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write!(f, "}}")
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}
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}
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pub fn debug_layout(func: &Func, layout: &FunctionLayout) {
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let custom = LayoutPrinter(Cell::default(), layout);
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println!("----- code layout");
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println!("{}", ir::pretty::func_to_string(func, &custom));
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dbg!(layout);
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}
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@ -5,46 +5,6 @@
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//! Then, all IR basic blocks and statements are lowered in a straightforward way.
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//! No optimizations are done. There is some basic register allocation.
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//!
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//! # Register allocation
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//!
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//! Register allocation is not very smart, but also not too stupid. It tries to put SSA
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//! registers into machine registers as much as possible.
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//!
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//! ```text
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//! bb0:
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//! %0 = 0
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//! %1 = 1
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//! %2 = add %0 %1
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//! switch %2, then bb1, else bb2
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//!
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//! bb1:
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//! %3 = add %1, 1
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//!
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//! bb2:
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//! %4 = add %2, 2
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//! ```
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//!
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//! For all SSA registers, we establish their "point of last use". This is the bb,stmt where their last usage occurs.
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//!
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//! First, we establish a list of possible registers to allocate.
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//! Since we immediately alloca all parameters, all the param registers are free real estate.
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//! Also, `rbx` is always saved on the stack at the start and end.
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//!
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//! ```text
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//! rax, rbx, rdi, rsi, rcx, rdx, r8, r9
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//! ```
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//!
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//! This forms our priority list of registers.
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//!
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//! Every time a statement has a return value, we try to assign that SSA register into a new machine register.
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//! For this, we iterate through the register list above and find the first register that's free. If we see a register
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//! that is not used anymore at the current location, we throw it out and use that new slot.
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//!
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//! When codegening an SSA register, we look into a lookup table from SSA register to machine register/stack spill and use that.
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//!
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//! When the list above is full, we spill the register to the stack. This should be rare. If the register doesn't fit into a machine
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//! register, it's also spilled.
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//!
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//! ## Registers
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//! <https://gitlab.com/x86-psABIs/x86-64-ABI>
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//!
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@ -78,7 +38,10 @@ use iced_x86::{
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use parser::{Error, Span};
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use rustc_hash::FxHashMap;
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use crate::Result;
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use crate::{
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registers::{MachineReg, RegValue},
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Result,
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};
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trait IcedErrExt {
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type T;
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@ -93,22 +56,6 @@ impl<T> IcedErrExt for Result<T, IcedError> {
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}
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}
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/// A machine register from our register list described in the module documentation.
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#[derive(Debug, Clone, Copy)]
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struct MachineReg(usize);
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#[derive(Debug, Clone, Copy)]
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enum RegValue {
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/// The SSA register contains an address on the stack.
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/// The offest is the offset from the start of the function.
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StackRelative { offset: u64 },
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/// The SSA register resides on the stack as it has been spilled.
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/// This should be rather rare in practice.
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Spilled { offset: u64 },
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/// The SSA register resides in a machine register.
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MachineReg(MachineReg),
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}
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struct AsmCtxt<'cx> {
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lcx: &'cx LoweringCx<'cx>,
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a: CodeAssembler,
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@ -276,6 +223,9 @@ impl<'cx> AsmCtxt<'cx> {
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pub fn generate_func<'cx>(lcx: &'cx LoweringCx<'cx>, func: &Func<'cx>) -> Result<Vec<u8>> {
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assert_eq!(func.arity, 0, "arguments??? in MY uwucc????");
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let layout = crate::registers::compute_layout(func);
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crate::registers::debug_layout(func, &layout);
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let fn_sp = func.def_span;
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let a = CodeAssembler::new(64).sp(fn_sp)?;
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